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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu_pre_norm_div.v] - Blame information for rev 258

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1 258 julius 
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  or1200_fpu_pre_norm_div                                     ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://opencores.org/project,or1k                           ////
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////                                                              ////
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////  Description                                                 ////
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////  pre-normalization entity for the division unit              ////
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////                                                              ////
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////  To Do:                                                      ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Original design (FPU100) -                            ////
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////        Jidan Al-eryani, jidan@gmx.net                        ////
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////      - Conv. to Verilog and inclusion in OR1200 -            ////
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////        Julius Baxter, julius@opencores.org                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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//  Copyright (C) 2006, 2010
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//
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//      This source file may be used and distributed without
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//      restriction provided that this copyright statement is not
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//      removed from the file and that any derivative work contains
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//      the original copyright notice and the associated disclaimer.
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//
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//              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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//      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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//      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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//      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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//      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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//      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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//      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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//      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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//      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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//      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
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//      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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//      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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//      POSSIBILITY OF SUCH DAMAGE.
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//
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module or1200_fpu_pre_norm_div
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  (
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   clk_i,
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   opa_i,
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   opb_i,
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   exp_10_o,
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   dvdnd_50_o,
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   dvsor_27_o
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   );
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   parameter FP_WIDTH = 32;
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   parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
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   parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
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   parameter FRAC_WIDTH = 23;
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   parameter EXP_WIDTH = 8;
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   parameter ZERO_VECTOR = 31'd0;
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   parameter INF = 31'b1111111100000000000000000000000;
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   parameter QNAN = 31'b1111111110000000000000000000000;
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   parameter SNAN = 31'b1111111100000000000000000000001;
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   input clk_i;
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   input [FP_WIDTH-1:0] opa_i;
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   input [FP_WIDTH-1:0] opb_i;
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   output reg [EXP_WIDTH+1:0] exp_10_o;
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   output [2*(FRAC_WIDTH+2)-1:0] dvdnd_50_o;
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   output [FRAC_WIDTH+3:0]        dvsor_27_o;
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   wire [EXP_WIDTH-1:0]   s_expa;
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   wire [EXP_WIDTH-1:0]   s_expb;
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   wire [FRAC_WIDTH-1:0]          s_fracta;
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   wire [FRAC_WIDTH-1:0]          s_fractb;
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   wire [2*(FRAC_WIDTH+2)-1:0]    s_dvdnd_50_o;
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   wire [FRAC_WIDTH+3:0]          s_dvsor_27_o;
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   reg [5:0]                      s_dvd_zeros;
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   reg [5:0]                      s_div_zeros;
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   reg [EXP_WIDTH+1:0]            s_exp_10_o;
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   reg [EXP_WIDTH+1:0]            s_expa_in;
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   reg [EXP_WIDTH+1:0]            s_expb_in;
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   wire                          s_opa_dn, s_opb_dn;
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   wire [FRAC_WIDTH:0]            s_fracta_24;
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   wire [FRAC_WIDTH:0]            s_fractb_24;
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   assign s_expa = opa_i[30:23];
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   assign s_expb = opb_i[30:23];
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   assign s_fracta = opa_i[22:0];
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   assign s_fractb = opb_i[22:0];
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   assign dvdnd_50_o = s_dvdnd_50_o;
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   assign dvsor_27_o    = s_dvsor_27_o;
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   // Output Register
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   always @(posedge clk_i)
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     exp_10_o <= s_exp_10_o;
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   assign s_opa_dn = !(|s_expa);
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   assign s_opb_dn = !(|s_expb);
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   assign s_fracta_24 = {!s_opa_dn,s_fracta};
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   assign s_fractb_24 = {!s_opb_dn,s_fractb};
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   // count leading zeros
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   //s_dvd_zeros <= count_l_zeros( s_fracta_24 );
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   always @(s_fracta_24)
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     casex(s_fracta_24) // synopsys full_case parallel_case
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       24'b1???????????????????????: s_dvd_zeros <=  0;
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       24'b01??????????????????????: s_dvd_zeros <=  1;
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       24'b001?????????????????????: s_dvd_zeros <=  2;
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       24'b0001????????????????????: s_dvd_zeros <=  3;
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       24'b00001???????????????????: s_dvd_zeros <=  4;
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       24'b000001??????????????????: s_dvd_zeros <=  5;
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       24'b0000001?????????????????: s_dvd_zeros <=  6;
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       24'b00000001????????????????: s_dvd_zeros <=  7;
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       24'b000000001???????????????: s_dvd_zeros <=  8;
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       24'b0000000001??????????????: s_dvd_zeros <=  9;
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       24'b00000000001?????????????: s_dvd_zeros <=  10;
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       24'b000000000001????????????: s_dvd_zeros <=  11;
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       24'b0000000000001???????????: s_dvd_zeros <=  12;
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       24'b00000000000001??????????: s_dvd_zeros <=  13;
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       24'b000000000000001?????????: s_dvd_zeros <=  14;
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       24'b0000000000000001????????: s_dvd_zeros <=  15;
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       24'b00000000000000001???????: s_dvd_zeros <=  16;
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       24'b000000000000000001??????: s_dvd_zeros <=  17;
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       24'b0000000000000000001?????: s_dvd_zeros <=  18;
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       24'b00000000000000000001????: s_dvd_zeros <=  19;
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       24'b000000000000000000001???: s_dvd_zeros <=  20;
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       24'b0000000000000000000001??: s_dvd_zeros <=  21;
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       24'b00000000000000000000001?: s_dvd_zeros <=  22;
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       24'b000000000000000000000001: s_dvd_zeros <=  23;
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       24'b000000000000000000000000: s_dvd_zeros <=  24;
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     endcase
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   //s_div_zeros <= count_l_zeros( s_fractb_24 );
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   always @(s_fractb_24)
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     casex(s_fractb_24) // synopsys full_case parallel_case
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       24'b1???????????????????????: s_div_zeros <=  0;
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       24'b01??????????????????????: s_div_zeros <=  1;
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       24'b001?????????????????????: s_div_zeros <=  2;
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       24'b0001????????????????????: s_div_zeros <=  3;
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       24'b00001???????????????????: s_div_zeros <=  4;
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       24'b000001??????????????????: s_div_zeros <=  5;
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       24'b0000001?????????????????: s_div_zeros <=  6;
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       24'b00000001????????????????: s_div_zeros <=  7;
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       24'b000000001???????????????: s_div_zeros <=  8;
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       24'b0000000001??????????????: s_div_zeros <=  9;
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       24'b00000000001?????????????: s_div_zeros <=  10;
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       24'b000000000001????????????: s_div_zeros <=  11;
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       24'b0000000000001???????????: s_div_zeros <=  12;
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       24'b00000000000001??????????: s_div_zeros <=  13;
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       24'b000000000000001?????????: s_div_zeros <=  14;
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       24'b0000000000000001????????: s_div_zeros <=  15;
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       24'b00000000000000001???????: s_div_zeros <=  16;
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       24'b000000000000000001??????: s_div_zeros <=  17;
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       24'b0000000000000000001?????: s_div_zeros <=  18;
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       24'b00000000000000000001????: s_div_zeros <=  19;
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       24'b000000000000000000001???: s_div_zeros <=  20;
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       24'b0000000000000000000001??: s_div_zeros <=  21;
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       24'b00000000000000000000001?: s_div_zeros <=  22;
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       24'b000000000000000000000001: s_div_zeros <=  23;
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       24'b000000000000000000000000: s_div_zeros <=  24;
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     endcase
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   // left-shift the dividend and divisor
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   wire [FRAC_WIDTH:0]            fracta_lshift_intermediate;
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   wire [FRAC_WIDTH:0]            fractb_lshift_intermediate;
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   assign fracta_lshift_intermediate = s_fracta_24 << s_dvd_zeros;
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   assign fractb_lshift_intermediate = s_fractb_24 << s_div_zeros;
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   assign s_dvdnd_50_o = {fracta_lshift_intermediate,26'd0};
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   assign s_dvsor_27_o = {3'd0,fractb_lshift_intermediate};
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   always @(posedge clk_i)
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     begin
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        // pre-calculate exponent
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        s_expa_in <= {2'd0,s_expa} + {9'd0,s_opa_dn};
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        s_expb_in <= {2'd0,s_expb} + {9'd0,s_opb_dn};
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        s_exp_10_o <= s_expa_in - s_expb_in + 10'b0001111111 -
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                      {4'd0,s_dvd_zeros} + {4'd0,s_div_zeros};
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     end
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endmodule // or1200_fpu_pre_norm_div
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