OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Blame information for rev 443

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's generate PC                                        ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 186 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  PC, interface to IC.                                        ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44 141 marcus.erl
// $Log: or1200_genpc.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Major update: 
47
// Structure reordered and bugs fixed. 
48 10 unneback
 
49
// synopsys translate_off
50
`include "timescale.v"
51
// synopsys translate_on
52
`include "or1200_defines.v"
53
 
54
module or1200_genpc(
55
        // Clock and reset
56
        clk, rst,
57
 
58
        // External i/f to IC
59
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
60
        icpu_rty_i, icpu_adr_i,
61
 
62
        // Internal i/f
63 141 marcus.erl
        pre_branch_op, branch_op, except_type, except_prefix,
64
        id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
65
        flag, flagforw, ex_branch_taken, except_start,
66
        epcr, spr_dat_i, spr_pc_we, genpc_refetch,
67
        genpc_freeze, no_more_dslot
68 10 unneback
);
69
 
70
//
71
// I/O
72
//
73
 
74
//
75
// Clock and reset
76
//
77
input                           clk;
78
input                           rst;
79
 
80
//
81
// External i/f to IC
82
//
83
output  [31:0]                   icpu_adr_o;
84
output                          icpu_cycstb_o;
85
output  [3:0]                    icpu_sel_o;
86
output  [3:0]                    icpu_tag_o;
87
input                           icpu_rty_i;
88
input   [31:0]                   icpu_adr_i;
89
 
90
//
91
// Internal i/f
92
//
93 141 marcus.erl
input   [`OR1200_BRANCHOP_WIDTH-1:0]    pre_branch_op;
94 10 unneback
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
95
input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
96
input                                   except_prefix;
97 141 marcus.erl
input   [31:2]                  id_branch_addrtarget;
98
input   [31:2]                  ex_branch_addrtarget;
99
input   [31:0]                   muxed_b;
100
input   [31:0]                   operand_b;
101 10 unneback
input                           flag;
102 141 marcus.erl
input                           flagforw;
103
output                          ex_branch_taken;
104 10 unneback
input                           except_start;
105
input   [31:0]                   epcr;
106
input   [31:0]                   spr_dat_i;
107
input                           spr_pc_we;
108
input                           genpc_refetch;
109
input                           genpc_freeze;
110
input                           no_more_dslot;
111
 
112
//
113
// Internal wires and regs
114
//
115 141 marcus.erl
reg     [31:2]                  pcreg_default;
116
wire    [31:0]                   pcreg_boot;
117
reg                             pcreg_select;
118 10 unneback
reg     [31:2]                  pcreg;
119
reg     [31:0]                   pc;
120 186 julius
// Set in event of jump or taken branch   
121
reg                             ex_branch_taken;
122 10 unneback
reg                             genpc_refetch_r;
123
 
124 186 julius
   //
125
   // Address of insn to be fecthed
126
   //
127
   assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we
128
                       & (icpu_rty_i | genpc_refetch) ?
129
                       icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
130 10 unneback
 
131 186 julius
   //
132
   // Control access to IC subsystem
133
   //
134
   assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i));
135
   assign icpu_sel_o = 4'b1111;
136
   assign icpu_tag_o = `OR1200_ITAG_NI;
137 10 unneback
 
138 186 julius
   //
139
   // genpc_freeze_r
140
   //
141 358 julius
   always @(posedge clk or `OR1200_RST_EVENT rst)
142
     if (rst == `OR1200_RST_VALUE)
143 258 julius
       genpc_refetch_r <=  1'b0;
144 186 julius
     else if (genpc_refetch)
145 258 julius
       genpc_refetch_r <=  1'b1;
146 186 julius
     else
147 258 julius
       genpc_refetch_r <=  1'b0;
148 10 unneback
 
149 186 julius
   //
150
   // Async calculation of new PC value. This value is used for addressing the
151
   // IC.
152
   //
153
   always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type
154
            or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or
155
            except_prefix)
156
     begin
157 364 julius
        casez ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
158 186 julius
          {2'b00, `OR1200_BRANCHOP_NOP}: begin
159
             pc = {pcreg + 30'd1, 2'b0};
160
             ex_branch_taken = 1'b0;
161
          end
162
          {2'b00, `OR1200_BRANCHOP_J}: begin
163 10 unneback
`ifdef OR1200_VERBOSE
164 186 julius
             // synopsys translate_off
165
             $display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h"
166
                      , $time, ex_branch_addrtarget);
167
             // synopsys translate_on
168 10 unneback
`endif
169 186 julius
             pc = {ex_branch_addrtarget, 2'b00};
170
             ex_branch_taken = 1'b1;
171
          end
172
          {2'b00, `OR1200_BRANCHOP_JR}: begin
173 10 unneback
`ifdef OR1200_VERBOSE
174 186 julius
             // synopsys translate_off
175
             $display("%t: BRANCHOP_JR: pc <= operand_b %h",
176
                      $time, operand_b);
177
             // synopsys translate_on
178 10 unneback
`endif
179 186 julius
             pc = operand_b;
180
             ex_branch_taken = 1'b1;
181
          end
182
          {2'b00, `OR1200_BRANCHOP_BF}:
183
            if (flag) begin
184 10 unneback
`ifdef OR1200_VERBOSE
185 186 julius
               // synopsys translate_off
186
               $display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h",
187
                        $time, ex_branch_addrtarget);
188
               // synopsys translate_on
189 10 unneback
`endif
190 186 julius
               pc = {ex_branch_addrtarget, 2'b00};
191
               ex_branch_taken = 1'b1;
192
            end
193
            else begin
194 10 unneback
`ifdef OR1200_VERBOSE
195 186 julius
               // synopsys translate_off
196
               $display("%t: BRANCHOP_BF: not taken", $time);
197
               // synopsys translate_on
198 10 unneback
`endif
199 186 julius
               pc = {pcreg + 30'd1, 2'b0};
200
               ex_branch_taken = 1'b0;
201
            end
202
          {2'b00, `OR1200_BRANCHOP_BNF}:
203
            if (flag) begin
204 10 unneback
`ifdef OR1200_VERBOSE
205 186 julius
               // synopsys translate_off
206
               $display("%t: BRANCHOP_BNF: not taken", $time);
207
               // synopsys translate_on
208 10 unneback
`endif
209 186 julius
               pc = {pcreg + 30'd1, 2'b0};
210
               ex_branch_taken = 1'b0;
211
            end
212
            else begin
213 10 unneback
`ifdef OR1200_VERBOSE
214 186 julius
               // synopsys translate_off
215
               $display("%t: BRANCHOP_BNF: pc <= ex_branch_addrtarget %h",
216
                        $time, ex_branch_addrtarget);
217
               // synopsys translate_on
218 10 unneback
`endif
219 186 julius
               pc = {ex_branch_addrtarget, 2'b00};
220
               ex_branch_taken = 1'b1;
221
            end
222
          {2'b00, `OR1200_BRANCHOP_RFE}: begin
223 10 unneback
`ifdef OR1200_VERBOSE
224 186 julius
             // synopsys translate_off
225
             $display("%t: BRANCHOP_RFE: pc <= epcr %h",
226
                      $time, epcr);
227
             // synopsys translate_on
228 10 unneback
`endif
229 186 julius
             pc = epcr;
230
             ex_branch_taken = 1'b1;
231
          end
232 364 julius
          {2'b01, 3'b???}: begin
233 10 unneback
`ifdef OR1200_VERBOSE
234 186 julius
             // synopsys translate_off
235
             $display("Starting exception: %h.", except_type);
236
             // synopsys translate_on
237 10 unneback
`endif
238 186 julius
             pc = {(except_prefix ?
239
                    `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P),
240
                   except_type, `OR1200_EXCEPT_V};
241
             ex_branch_taken = 1'b1;
242
          end
243
          default: begin
244 10 unneback
`ifdef OR1200_VERBOSE
245 186 julius
             // synopsys translate_off
246
             $display("l.mtspr writing into PC: %h.", spr_dat_i);
247
             // synopsys translate_on
248 10 unneback
`endif
249 186 julius
             pc = spr_dat_i;
250
             ex_branch_taken = 1'b0;
251
          end
252 10 unneback
        endcase
253 186 julius
     end
254 10 unneback
 
255 186 julius
   //
256
   // PC register
257
   //
258 358 julius
   always @(posedge clk or `OR1200_RST_EVENT rst)
259 186 julius
     // default value 
260 358 julius
     if (rst == `OR1200_RST_VALUE) begin
261 258 julius
        pcreg_default <=  `OR1200_BOOT_PCREG_DEFAULT; // jb
262
        pcreg_select <=  1'b1;// select async. value due to reset state
263 186 julius
     end
264
   // selected value (different from default) is written into FF after
265
   // reset state
266
     else if (pcreg_select) begin
267
        // dynamic value can only be assigned to FF out of reset! 
268 258 julius
        pcreg_default <=  pcreg_boot[31:2];
269
        pcreg_select <=  1'b0;          // select FF value 
270 186 julius
     end
271
     else if (spr_pc_we) begin
272 258 julius
        pcreg_default <=  spr_dat_i[31:2];
273 186 julius
     end
274
     else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i
275
              & !genpc_refetch) begin
276 258 julius
        pcreg_default <=  pc[31:2];
277 186 julius
     end
278 10 unneback
 
279 186 julius
   // select async. value for pcreg after reset - PC jumps to the address selected
280
   // after boot.
281 141 marcus.erl
   assign  pcreg_boot = `OR1200_BOOT_ADR; // changed JB
282
 
283 186 julius
   always @(pcreg_boot or pcreg_default or pcreg_select)
284
     if (pcreg_select)
285
       // async. value is selected due to reset state 
286
       pcreg = pcreg_boot[31:2];
287
     else
288
       // FF value is selected 2nd clock after reset state 
289
       pcreg = pcreg_default ;
290 141 marcus.erl
 
291 10 unneback
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.