URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Blame information for rev 168

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's generate PC                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, interface to IC.                                        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_genpc.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Structure reordered and bugs fixed. 
//
// Revision 1.10  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.9  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.7.4.3  2003/12/17 13:43:38  simons
// Exception prefix configuration changed.
//
// Revision 1.7.4.2  2003/12/04 23:44:31  lampret
// Static exception prefix.
//
// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
//
// Revision 1.7  2003/04/20 22:23:57  lampret
// No functional change. Only added customization for exception vectors.
//
// Revision 1.6  2002/03/29 15:16:55  lampret
// Some of the warnings fixed.
//
// Revision 1.5  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.3  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_genpc(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
        icpu_rty_i, icpu_adr_i,
 
        // Internal i/f
        pre_branch_op, branch_op, except_type, except_prefix,
        id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
        flag, flagforw, ex_branch_taken, except_start,
        epcr, spr_dat_i, spr_pc_we, genpc_refetch,
        genpc_freeze, no_more_dslot
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
output  [31:0]                   icpu_adr_o;
output                          icpu_cycstb_o;
output  [3:0]                    icpu_sel_o;
output  [3:0]                    icpu_tag_o;
input                           icpu_rty_i;
input   [31:0]                   icpu_adr_i;
 
//
// Internal i/f
//
input   [`OR1200_BRANCHOP_WIDTH-1:0]    pre_branch_op;
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
input                                   except_prefix;
input   [31:2]                  id_branch_addrtarget;
input   [31:2]                  ex_branch_addrtarget;
input   [31:0]                   muxed_b;
input   [31:0]                   operand_b;
input                           flag;
input                           flagforw;
output                          ex_branch_taken;
input                           except_start;
input   [31:0]                   epcr;
input   [31:0]                   spr_dat_i;
input                           spr_pc_we;
input                           genpc_refetch;
input                           genpc_freeze;
input                           no_more_dslot;
 
//
// Internal wires and regs
//
reg     [31:2]                  pcreg_default;
wire    [31:0]                   pcreg_boot;
reg                             pcreg_select;
reg     [31:2]                  pcreg;
reg     [31:0]                   pc;
reg                             ex_branch_taken;        /* Set to in case of jump or taken branch */
reg                             genpc_refetch_r;
 
//
// Address of insn to be fecthed
//
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
 
//
// Control access to IC subsystem
//
assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i));
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
 
//
// genpc_freeze_r
//
always @(posedge clk or posedge rst)
        if (rst)
                genpc_refetch_r <= #1 1'b0;
        else if (genpc_refetch)
                genpc_refetch_r <= #1 1'b1;
        else
                genpc_refetch_r <= #1 1'b0;
 
//
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type
        or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
        casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
                {2'b00, `OR1200_BRANCHOP_NOP}: begin
                        pc = {pcreg + 30'd1, 2'b0};
                        ex_branch_taken = 1'b0;
                end
                {2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
// synopsys translate_on
`endif
                        pc = {ex_branch_addrtarget, 2'b00};
                        ex_branch_taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_JR: pc <= operand_b %h", $time, operand_b);
// synopsys translate_on
`endif
                        pc = operand_b;
                        ex_branch_taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BF}:
                        if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
// synopsys translate_on
`endif
                                pc = {ex_branch_addrtarget, 2'b00};
                                ex_branch_taken = 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
                                pc = {pcreg + 30'd1, 2'b0};
                                ex_branch_taken = 1'b0;
                        end
                {2'b00, `OR1200_BRANCHOP_BNF}:
                        if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
                                pc = {pcreg + 30'd1, 2'b0};
                                ex_branch_taken = 1'b0;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
// synopsys translate_on
`endif
                                pc = {ex_branch_addrtarget, 2'b00};
                                ex_branch_taken = 1'b1;
                        end
                {2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
// synopsys translate_on
`endif
                        pc = epcr;
                        ex_branch_taken = 1'b1;
                end
                {2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
                        pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
                        ex_branch_taken = 1'b1;
                end
                default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
                        pc = spr_dat_i;
                        ex_branch_taken = 1'b0;
                end
        endcase
end
 
//
// PC register
//
always @(posedge clk or posedge rst)
        // default value 
        if (rst) begin
           //pcreg_default <= #1 30'd63;
           pcreg_default <= #1 /*30'd63 */ `OR1200_BOOT_PCREG_DEFAULT; // jb
           pcreg_select <= #1 1'b1;             // select async. value due to reset state
        end
        // selected value (different from default) is written into FF after reset state
        else if (pcreg_select) begin
                pcreg_default <= #1 pcreg_boot[31:2];   // dynamic value can only be assigned to FF out of reset! 
                pcreg_select <= #1 1'b0;                // select FF value 
        end
        else if (spr_pc_we) begin
                pcreg_default <= #1 spr_dat_i[31:2];
        end
        else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch) begin
                pcreg_default <= #1 pc[31:2];
        end
 
// select async. value for pcreg after reset - PC jumps to the address selected after boot! 
//assign  pcreg_boot = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1;
   assign  pcreg_boot = `OR1200_BOOT_ADR; // changed JB
 
always @(pcreg_boot or pcreg_default or pcreg_select)
    if (pcreg_select)
        pcreg = pcreg_boot[31:2];       // async. value is selected due to reset state 
    else
        pcreg = pcreg_default ;         // FF value is selected 2nd clock after reset state 
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's generate PC ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PC, interface to IC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	141	marcus.erl	`// $Log: or1200_genpc.v,v $`
47			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
48			`// Major update:`
49			`// Structure reordered and bugs fixed.`
50			`//`
51			`// Revision 1.10 2004/06/08 18:17:36 lampret`
52			`// Non-functional changes. Coding style fixes.`
53			`//`
54	10	unneback	`// Revision 1.9 2004/04/05 08:29:57 lampret`
55			`// Merged branch_qmem into main tree.`
56			`//`
57			`// Revision 1.7.4.3 2003/12/17 13:43:38 simons`
58			`// Exception prefix configuration changed.`
59			`//`
60			`// Revision 1.7.4.2 2003/12/04 23:44:31 lampret`
61			`// Static exception prefix.`
62			`//`
63			`// Revision 1.7.4.1 2003/07/08 15:36:37 lampret`
64			`// Added embedded memory QMEM.`
65			`//`
66			`// Revision 1.7 2003/04/20 22:23:57 lampret`
67			`// No functional change. Only added customization for exception vectors.`
68			`//`
69			`// Revision 1.6 2002/03/29 15:16:55 lampret`
70			`// Some of the warnings fixed.`
71			`//`
72			`// Revision 1.5 2002/02/11 04:33:17 lampret`
73			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
74			`//`
75			`// Revision 1.4 2002/01/28 01:16:00 lampret`
76			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
77			`//`
78			`// Revision 1.3 2002/01/18 07:56:00 lampret`
79			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
80			`//`
81			`// Revision 1.2 2002/01/14 06:18:22 lampret`
82			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
83			`//`
84			`// Revision 1.1 2002/01/03 08:16:15 lampret`
85			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
86			`//`
87			`// Revision 1.10 2001/11/20 18:46:15 simons`
88			`// Break point bug fixed`
89			`//`
90			`// Revision 1.9 2001/11/18 09:58:28 lampret`
91			`// Fixed some l.trap typos.`
92			`//`
93			`// Revision 1.8 2001/11/18 08:36:28 lampret`
94			`// For GDB changed single stepping and disabled trap exception.`
95			`//`
96			`// Revision 1.7 2001/10/21 17:57:16 lampret`
97			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
98			`//`
99			`// Revision 1.6 2001/10/14 13:12:09 lampret`
100			`// MP3 version.`
101			`//`
102			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
103			`// no message`
104			`//`
105			`// Revision 1.1 2001/08/09 13:39:33 lampret`
106			`// Major clean-up.`
107			`//`
108			`//`
109
110			`// synopsys translate_off`
111			`include "timescale.v"
112			`// synopsys translate_on`
113			`include "or1200_defines.v"
114
115			`module or1200_genpc(`
116			`// Clock and reset`
117			`clk, rst,`
118
119			`// External i/f to IC`
120			`icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,`
121			`icpu_rty_i, icpu_adr_i,`
122
123			`// Internal i/f`
124	141	marcus.erl	`pre_branch_op, branch_op, except_type, except_prefix,`
125			`id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,`
126			`flag, flagforw, ex_branch_taken, except_start,`
127			`epcr, spr_dat_i, spr_pc_we, genpc_refetch,`
128			`genpc_freeze, no_more_dslot`
129	10	unneback	`);`
130
131			`//`
132			`// I/O`
133			`//`
134
135			`//`
136			`// Clock and reset`
137			`//`
138			`input clk;`
139			`input rst;`
140
141			`//`
142			`// External i/f to IC`
143			`//`
144			`output [31:0] icpu_adr_o;`
145			`output icpu_cycstb_o;`
146			`output [3:0] icpu_sel_o;`
147			`output [3:0] icpu_tag_o;`
148			`input icpu_rty_i;`
149			`input [31:0] icpu_adr_i;`
150
151			`//`
152			`// Internal i/f`
153			`//`
154	141	marcus.erl	input [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
155	10	unneback	input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
156			input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
157			`input except_prefix;`
158	141	marcus.erl	`input [31:2] id_branch_addrtarget;`
159			`input [31:2] ex_branch_addrtarget;`
160			`input [31:0] muxed_b;`
161			`input [31:0] operand_b;`
162	10	unneback	`input flag;`
163	141	marcus.erl	`input flagforw;`
164			`output ex_branch_taken;`
165	10	unneback	`input except_start;`
166			`input [31:0] epcr;`
167			`input [31:0] spr_dat_i;`
168			`input spr_pc_we;`
169			`input genpc_refetch;`
170			`input genpc_freeze;`
171			`input no_more_dslot;`
172
173			`//`
174			`// Internal wires and regs`
175			`//`
176	141	marcus.erl	`reg [31:2] pcreg_default;`
177			`wire [31:0] pcreg_boot;`
178			`reg pcreg_select;`
179	10	unneback	`reg [31:2] pcreg;`
180			`reg [31:0] pc;`
181	141	marcus.erl	`reg ex_branch_taken; /* Set to in case of jump or taken branch */`
182	10	unneback	`reg genpc_refetch_r;`
183
184			`//`
185			`// Address of insn to be fecthed`
186			`//`
187	141	marcus.erl	`assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i \| genpc_refetch) ? icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken\|spr_pc_we};`
188	10	unneback
189			`//`
190			`// Control access to IC subsystem`
191			`//`
192	141	marcus.erl	`assign icpu_cycstb_o = ~(genpc_freeze \| (\|pre_branch_op && !icpu_rty_i));`
193	10	unneback	`assign icpu_sel_o = 4'b1111;`
194			assign icpu_tag_o = `OR1200_ITAG_NI;
195
196			`//`
197			`// genpc_freeze_r`
198			`//`
199			`always @(posedge clk or posedge rst)`
200			`if (rst)`
201			`genpc_refetch_r <= #1 1'b0;`
202			`else if (genpc_refetch)`
203			`genpc_refetch_r <= #1 1'b1;`
204			`else`
205			`genpc_refetch_r <= #1 1'b0;`
206
207			`//`
208			`// Async calculation of new PC value. This value is used for addressing the IC.`
209			`//`
210	141	marcus.erl	`always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type`
211			`or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or except_prefix) begin`
212	10	unneback	`casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case`
213			{2'b00, `OR1200_BRANCHOP_NOP}: begin
214			`pc = {pcreg + 30'd1, 2'b0};`
215	141	marcus.erl	`ex_branch_taken = 1'b0;`
216	10	unneback	`end`
217			{2'b00, `OR1200_BRANCHOP_J}: begin
218			`ifdef OR1200_VERBOSE
219			`// synopsys translate_off`
220	141	marcus.erl	`$display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);`
221	10	unneback	`// synopsys translate_on`
222			`endif
223	141	marcus.erl	`pc = {ex_branch_addrtarget, 2'b00};`
224			`ex_branch_taken = 1'b1;`
225	10	unneback	`end`
226			{2'b00, `OR1200_BRANCHOP_JR}: begin
227			`ifdef OR1200_VERBOSE
228			`// synopsys translate_off`
229	141	marcus.erl	`$display("%t: BRANCHOP_JR: pc <= operand_b %h", $time, operand_b);`
230	10	unneback	`// synopsys translate_on`
231			`endif
232	141	marcus.erl	`pc = operand_b;`
233			`ex_branch_taken = 1'b1;`
234	10	unneback	`end`
235			{2'b00, `OR1200_BRANCHOP_BF}:
236			`if (flag) begin`
237			`ifdef OR1200_VERBOSE
238			`// synopsys translate_off`
239	141	marcus.erl	`$display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);`
240	10	unneback	`// synopsys translate_on`
241			`endif
242	141	marcus.erl	`pc = {ex_branch_addrtarget, 2'b00};`
243			`ex_branch_taken = 1'b1;`
244	10	unneback	`end`
245			`else begin`
246			`ifdef OR1200_VERBOSE
247			`// synopsys translate_off`
248			`$display("%t: BRANCHOP_BF: not taken", $time);`
249			`// synopsys translate_on`
250			`endif
251			`pc = {pcreg + 30'd1, 2'b0};`
252	141	marcus.erl	`ex_branch_taken = 1'b0;`
253	10	unneback	`end`
254			{2'b00, `OR1200_BRANCHOP_BNF}:
255			`if (flag) begin`
256			`ifdef OR1200_VERBOSE
257			`// synopsys translate_off`
258			`$display("%t: BRANCHOP_BNF: not taken", $time);`
259			`// synopsys translate_on`
260			`endif
261	141	marcus.erl	`pc = {pcreg + 30'd1, 2'b0};`
262			`ex_branch_taken = 1'b0;`
263	10	unneback	`end`
264			`else begin`
265			`ifdef OR1200_VERBOSE
266			`// synopsys translate_off`
267	141	marcus.erl	`$display("%t: BRANCHOP_BNF: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);`
268	10	unneback	`// synopsys translate_on`
269			`endif
270	141	marcus.erl	`pc = {ex_branch_addrtarget, 2'b00};`
271			`ex_branch_taken = 1'b1;`
272	10	unneback	`end`
273			{2'b00, `OR1200_BRANCHOP_RFE}: begin
274			`ifdef OR1200_VERBOSE
275			`// synopsys translate_off`
276			`$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);`
277			`// synopsys translate_on`
278			`endif
279			`pc = epcr;`
280	141	marcus.erl	`ex_branch_taken = 1'b1;`
281	10	unneback	`end`
282			`{2'b01, 3'bxxx}: begin`
283			`ifdef OR1200_VERBOSE
284			`// synopsys translate_off`
285			`$display("Starting exception: %h.", except_type);`
286			`// synopsys translate_on`
287			`endif
288			pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
289	141	marcus.erl	`ex_branch_taken = 1'b1;`
290	10	unneback	`end`
291			`default: begin`
292			`ifdef OR1200_VERBOSE
293			`// synopsys translate_off`
294			`$display("l.mtspr writing into PC: %h.", spr_dat_i);`
295			`// synopsys translate_on`
296			`endif
297			`pc = spr_dat_i;`
298	141	marcus.erl	`ex_branch_taken = 1'b0;`
299	10	unneback	`end`
300			`endcase`
301			`end`
302
303			`//`
304			`// PC register`
305			`//`
306			`always @(posedge clk or posedge rst)`
307	141	marcus.erl	`// default value`
308			`if (rst) begin`
309			`//pcreg_default <= #1 30'd63;`
310			pcreg_default <= #1 /30'd63 / `OR1200_BOOT_PCREG_DEFAULT; // jb
311			`pcreg_select <= #1 1'b1; // select async. value due to reset state`
312			`end`
313			`// selected value (different from default) is written into FF after reset state`
314			`else if (pcreg_select) begin`
315			`pcreg_default <= #1 pcreg_boot[31:2]; // dynamic value can only be assigned to FF out of reset!`
316			`pcreg_select <= #1 1'b0; // select FF value`
317			`end`
318			`else if (spr_pc_we) begin`
319			`pcreg_default <= #1 spr_dat_i[31:2];`
320			`end`
321			`else if (no_more_dslot \| except_start \| !genpc_freeze & !icpu_rty_i & !genpc_refetch) begin`
322			`pcreg_default <= #1 pc[31:2];`
323			`end`
324	10	unneback
325	141	marcus.erl	`// select async. value for pcreg after reset - PC jumps to the address selected after boot!`
326			//assign pcreg_boot = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1;
327			assign pcreg_boot = `OR1200_BOOT_ADR; // changed JB
328
329			`always @(pcreg_boot or pcreg_default or pcreg_select)`
330			`if (pcreg_select)`
331			`pcreg = pcreg_boot[31:2]; // async. value is selected due to reset state`
332			`else`
333			`pcreg = pcreg_default ; // FF value is selected 2nd clock after reset state`
334
335	10	unneback	`endmodule`

Browse

Tools

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Blame information for rev 168