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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Blame information for rev 146

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's generate PC                                        ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  PC, interface to IC.                                        ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
46 141 marcus.erl
// $Log: or1200_genpc.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// Major update: 
49
// Structure reordered and bugs fixed. 
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//
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// Revision 1.10  2004/06/08 18:17:36  lampret
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// Non-functional changes. Coding style fixes.
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//
54 10 unneback
// Revision 1.9  2004/04/05 08:29:57  lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.7.4.3  2003/12/17 13:43:38  simons
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// Exception prefix configuration changed.
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//
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// Revision 1.7.4.2  2003/12/04 23:44:31  lampret
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// Static exception prefix.
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//
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// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.7  2003/04/20 22:23:57  lampret
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// No functional change. Only added customization for exception vectors.
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//
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// Revision 1.6  2002/03/29 15:16:55  lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5  2002/02/11 04:33:17  lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4  2002/01/28 01:16:00  lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
77
//
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// Revision 1.3  2002/01/18 07:56:00  lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.2  2002/01/14 06:18:22  lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10  2001/11/20 18:46:15  simons
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// Break point bug fixed
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//
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// Revision 1.9  2001/11/18 09:58:28  lampret
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// Fixed some l.trap typos.
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//
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// Revision 1.8  2001/11/18 08:36:28  lampret
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// For GDB changed single stepping and disabled trap exception.
95
//
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// Revision 1.7  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
98
//
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// Revision 1.6  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.1  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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//
109
 
110
// synopsys translate_off
111
`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
114
 
115
module or1200_genpc(
116
        // Clock and reset
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        clk, rst,
118
 
119
        // External i/f to IC
120
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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        icpu_rty_i, icpu_adr_i,
122
 
123
        // Internal i/f
124 141 marcus.erl
        pre_branch_op, branch_op, except_type, except_prefix,
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        id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
126
        flag, flagforw, ex_branch_taken, except_start,
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        epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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        genpc_freeze, no_more_dslot
129 10 unneback
);
130
 
131
//
132
// I/O
133
//
134
 
135
//
136
// Clock and reset
137
//
138
input                           clk;
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input                           rst;
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141
//
142
// External i/f to IC
143
//
144
output  [31:0]                   icpu_adr_o;
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output                          icpu_cycstb_o;
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output  [3:0]                    icpu_sel_o;
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output  [3:0]                    icpu_tag_o;
148
input                           icpu_rty_i;
149
input   [31:0]                   icpu_adr_i;
150
 
151
//
152
// Internal i/f
153
//
154 141 marcus.erl
input   [`OR1200_BRANCHOP_WIDTH-1:0]    pre_branch_op;
155 10 unneback
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
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input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
157
input                                   except_prefix;
158 141 marcus.erl
input   [31:2]                  id_branch_addrtarget;
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input   [31:2]                  ex_branch_addrtarget;
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input   [31:0]                   muxed_b;
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input   [31:0]                   operand_b;
162 10 unneback
input                           flag;
163 141 marcus.erl
input                           flagforw;
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output                          ex_branch_taken;
165 10 unneback
input                           except_start;
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input   [31:0]                   epcr;
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input   [31:0]                   spr_dat_i;
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input                           spr_pc_we;
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input                           genpc_refetch;
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input                           genpc_freeze;
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input                           no_more_dslot;
172
 
173
//
174
// Internal wires and regs
175
//
176 141 marcus.erl
reg     [31:2]                  pcreg_default;
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wire    [31:0]                   pcreg_boot;
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reg                             pcreg_select;
179 10 unneback
reg     [31:2]                  pcreg;
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reg     [31:0]                   pc;
181 141 marcus.erl
reg                             ex_branch_taken;        /* Set to in case of jump or taken branch */
182 10 unneback
reg                             genpc_refetch_r;
183
 
184
//
185
// Address of insn to be fecthed
186
//
187 141 marcus.erl
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
188 10 unneback
 
189
//
190
// Control access to IC subsystem
191
//
192 141 marcus.erl
assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i));
193 10 unneback
assign icpu_sel_o = 4'b1111;
194
assign icpu_tag_o = `OR1200_ITAG_NI;
195
 
196
//
197
// genpc_freeze_r
198
//
199
always @(posedge clk or posedge rst)
200
        if (rst)
201
                genpc_refetch_r <= #1 1'b0;
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        else if (genpc_refetch)
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                genpc_refetch_r <= #1 1'b1;
204
        else
205
                genpc_refetch_r <= #1 1'b0;
206
 
207
//
208
// Async calculation of new PC value. This value is used for addressing the IC.
209
//
210 141 marcus.erl
always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type
211
        or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
212 10 unneback
        casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
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                {2'b00, `OR1200_BRANCHOP_NOP}: begin
214
                        pc = {pcreg + 30'd1, 2'b0};
215 141 marcus.erl
                        ex_branch_taken = 1'b0;
216 10 unneback
                end
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                {2'b00, `OR1200_BRANCHOP_J}: begin
218
`ifdef OR1200_VERBOSE
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// synopsys translate_off
220 141 marcus.erl
                        $display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
221 10 unneback
// synopsys translate_on
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`endif
223 141 marcus.erl
                        pc = {ex_branch_addrtarget, 2'b00};
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                        ex_branch_taken = 1'b1;
225 10 unneback
                end
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                {2'b00, `OR1200_BRANCHOP_JR}: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
229 141 marcus.erl
                        $display("%t: BRANCHOP_JR: pc <= operand_b %h", $time, operand_b);
230 10 unneback
// synopsys translate_on
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`endif
232 141 marcus.erl
                        pc = operand_b;
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                        ex_branch_taken = 1'b1;
234 10 unneback
                end
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                {2'b00, `OR1200_BRANCHOP_BF}:
236
                        if (flag) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
239 141 marcus.erl
                                $display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
240 10 unneback
// synopsys translate_on
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`endif
242 141 marcus.erl
                                pc = {ex_branch_addrtarget, 2'b00};
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                                ex_branch_taken = 1'b1;
244 10 unneback
                        end
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                        else begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                                $display("%t: BRANCHOP_BF: not taken", $time);
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// synopsys translate_on
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`endif
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                                pc = {pcreg + 30'd1, 2'b0};
252 141 marcus.erl
                                ex_branch_taken = 1'b0;
253 10 unneback
                        end
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                {2'b00, `OR1200_BRANCHOP_BNF}:
255
                        if (flag) begin
256
`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                                $display("%t: BRANCHOP_BNF: not taken", $time);
259
// synopsys translate_on
260
`endif
261 141 marcus.erl
                                pc = {pcreg + 30'd1, 2'b0};
262
                                ex_branch_taken = 1'b0;
263 10 unneback
                        end
264
                        else begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
267 141 marcus.erl
                                $display("%t: BRANCHOP_BNF: pc <= ex_branch_addrtarget %h", $time, ex_branch_addrtarget);
268 10 unneback
// synopsys translate_on
269
`endif
270 141 marcus.erl
                                pc = {ex_branch_addrtarget, 2'b00};
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                                ex_branch_taken = 1'b1;
272 10 unneback
                        end
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                {2'b00, `OR1200_BRANCHOP_RFE}: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                        $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
277
// synopsys translate_on
278
`endif
279
                        pc = epcr;
280 141 marcus.erl
                        ex_branch_taken = 1'b1;
281 10 unneback
                end
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                {2'b01, 3'bxxx}: begin
283
`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                        $display("Starting exception: %h.", except_type);
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// synopsys translate_on
287
`endif
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                        pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
289 141 marcus.erl
                        ex_branch_taken = 1'b1;
290 10 unneback
                end
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                default: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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                        $display("l.mtspr writing into PC: %h.", spr_dat_i);
295
// synopsys translate_on
296
`endif
297
                        pc = spr_dat_i;
298 141 marcus.erl
                        ex_branch_taken = 1'b0;
299 10 unneback
                end
300
        endcase
301
end
302
 
303
//
304
// PC register
305
//
306
always @(posedge clk or posedge rst)
307 141 marcus.erl
        // default value 
308
        if (rst) begin
309
           //pcreg_default <= #1 30'd63;
310
           pcreg_default <= #1 /*30'd63 */ `OR1200_BOOT_PCREG_DEFAULT; // jb
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           pcreg_select <= #1 1'b1;             // select async. value due to reset state
312
        end
313
        // selected value (different from default) is written into FF after reset state
314
        else if (pcreg_select) begin
315
                pcreg_default <= #1 pcreg_boot[31:2];   // dynamic value can only be assigned to FF out of reset! 
316
                pcreg_select <= #1 1'b0;                // select FF value 
317
        end
318
        else if (spr_pc_we) begin
319
                pcreg_default <= #1 spr_dat_i[31:2];
320
        end
321
        else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch) begin
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                pcreg_default <= #1 pc[31:2];
323
        end
324 10 unneback
 
325 141 marcus.erl
// select async. value for pcreg after reset - PC jumps to the address selected after boot! 
326
//assign  pcreg_boot = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1;
327
   assign  pcreg_boot = `OR1200_BOOT_ADR; // changed JB
328
 
329
always @(pcreg_boot or pcreg_default or pcreg_select)
330
    if (pcreg_select)
331
        pcreg = pcreg_boot[31:2];       // async. value is selected due to reset state 
332
    else
333
        pcreg = pcreg_default ;         // FF value is selected 2nd clock after reset state 
334
 
335 10 unneback
endmodule

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