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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_gmultp2_32x32.v] - Blame information for rev 791

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic 32x32 multiplier                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  Generic 32x32 multiplier with pipeline stages.              ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_gmultp2_32x32.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// No update 
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
// 32x32 multiplier, no input/output registers
// Registers inside Wallace trees every 8 full adder levels,
// with first pipeline after level 4
 
`ifdef OR1200_GENERIC_MULTP2_32X32
 
`define OR1200_W 32
`define OR1200_WW 64
 
module or1200_gmultp2_32x32 ( X, Y, CLK, RST, P );
 
input   [`OR1200_W-1:0]  X;
input   [`OR1200_W-1:0]  Y;
input           CLK;
input           RST;
output  [`OR1200_WW-1:0]  P;
 
reg     [`OR1200_WW-1:0]  p0;
reg     [`OR1200_WW-1:0]  p1;
integer                   xi;
integer                   yi;
 
//
// Conversion unsigned to signed
//
always @(X)
        xi = X;
 
//
// Conversion unsigned to signed
//
always @(Y)
        yi = Y;
 
//
// First multiply stage
//
always @(posedge CLK or `OR1200_RST_EVENT RST)
        if (RST == `OR1200_RST_VALUE)
                p0 <= `OR1200_WW'b0;
        else
                p0 <=  xi * yi;
 
//
// Second multiply stage
//
always @(posedge CLK or `OR1200_RST_EVENT RST)
        if (RST == `OR1200_RST_VALUE)
                p1 <= `OR1200_WW'b0;
        else
                p1 <=  p0;
 
assign P = p1;
 
endmodule
 
`endif

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic 32x32 multiplier ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6	481	julius	`//// http://www.opencores.org/project,or1k ////`
7	10	unneback	`//// ////`
8			`//// Description ////`
9			`//// Generic 32x32 multiplier with pipeline stages. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	141	marcus.erl	`// $Log: or1200_gmultp2_32x32.v,v $`
47			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
48			`// No update`
49			`//`
50	10	unneback
51			`// synopsys translate_off`
52			`include "timescale.v"
53			`// synopsys translate_on`
54			`include "or1200_defines.v"
55
56			`// 32x32 multiplier, no input/output registers`
57			`// Registers inside Wallace trees every 8 full adder levels,`
58			`// with first pipeline after level 4`
59
60			`ifdef OR1200_GENERIC_MULTP2_32X32
61
62			`define OR1200_W 32
63			`define OR1200_WW 64
64
65			`module or1200_gmultp2_32x32 ( X, Y, CLK, RST, P );`
66
67			input [`OR1200_W-1:0] X;
68			input [`OR1200_W-1:0] Y;
69			`input CLK;`
70			`input RST;`
71			output [`OR1200_WW-1:0] P;
72
73			reg [`OR1200_WW-1:0] p0;
74			reg [`OR1200_WW-1:0] p1;
75			`integer xi;`
76			`integer yi;`
77
78			`//`
79			`// Conversion unsigned to signed`
80			`//`
81			`always @(X)`
82	364	julius	`xi = X;`
83	10	unneback
84			`//`
85			`// Conversion unsigned to signed`
86			`//`
87			`always @(Y)`
88	364	julius	`yi = Y;`
89
90	10	unneback	`//`
91			`// First multiply stage`
92			`//`
93	358	julius	always @(posedge CLK or `OR1200_RST_EVENT RST)
94			if (RST == `OR1200_RST_VALUE)
95	10	unneback	p0 <= `OR1200_WW'b0;
96			`else`
97	258	julius	`p0 <= xi * yi;`
98	10	unneback
99			`//`
100			`// Second multiply stage`
101			`//`
102	358	julius	always @(posedge CLK or `OR1200_RST_EVENT RST)
103			if (RST == `OR1200_RST_VALUE)
104	10	unneback	p1 <= `OR1200_WW'b0;
105			`else`
106	258	julius	`p1 <= p0;`
107	10	unneback
108			`assign P = p1;`
109
110			`endmodule`
111
112			`endif

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_gmultp2_32x32.v] - Blame information for rev 791