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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_gmultp2_32x32.v] - Blame information for rev 55

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic 32x32 multiplier                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Generic 32x32 multiplier with pipeline stages.              ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.4  2001/12/04 05:02:35  lampret
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
//
// Revision 1.3  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.2  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
// 32x32 multiplier, no input/output registers
// Registers inside Wallace trees every 8 full adder levels,
// with first pipeline after level 4
 
`ifdef OR1200_GENERIC_MULTP2_32X32
 
`define OR1200_W 32
`define OR1200_WW 64
 
module or1200_gmultp2_32x32 ( X, Y, CLK, RST, P );
 
input   [`OR1200_W-1:0]  X;
input   [`OR1200_W-1:0]  Y;
input           CLK;
input           RST;
output  [`OR1200_WW-1:0]  P;
 
reg     [`OR1200_WW-1:0]  p0;
reg     [`OR1200_WW-1:0]  p1;
integer                   xi;
integer                   yi;
 
//
// Conversion unsigned to signed
//
always @(X)
        xi <= X;
 
//
// Conversion unsigned to signed
//
always @(Y)
        yi <= Y;
 
//
// First multiply stage
//
always @(posedge CLK or posedge RST)
        if (RST)
                p0 <= `OR1200_WW'b0;
        else
                p0 <= #1 xi * yi;
 
//
// Second multiply stage
//
always @(posedge CLK or posedge RST)
        if (RST)
                p1 <= `OR1200_WW'b0;
        else
                p1 <= #1 p0;
 
assign P = p1;
 
endmodule
 
`endif

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic 32x32 multiplier ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Generic 32x32 multiplier with pipeline stages. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1 2002/01/03 08:16:15 lampret`
48			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
49			`//`
50			`// Revision 1.4 2001/12/04 05:02:35 lampret`
51			`// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32`
52			`//`
53			`// Revision 1.3 2001/10/21 17:57:16 lampret`
54			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
55			`//`
56			`// Revision 1.2 2001/10/14 13:12:09 lampret`
57			`// MP3 version.`
58			`//`
59			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
60			`// no message`
61			`//`
62			`// Revision 1.2 2001/08/09 13:39:33 lampret`
63			`// Major clean-up.`
64			`//`
65			`// Revision 1.1 2001/07/20 00:46:03 lampret`
66			`// Development version of RTL. Libraries are missing.`
67			`//`
68			`//`
69
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "or1200_defines.v"
74
75			`// 32x32 multiplier, no input/output registers`
76			`// Registers inside Wallace trees every 8 full adder levels,`
77			`// with first pipeline after level 4`
78
79			`ifdef OR1200_GENERIC_MULTP2_32X32
80
81			`define OR1200_W 32
82			`define OR1200_WW 64
83
84			`module or1200_gmultp2_32x32 ( X, Y, CLK, RST, P );`
85
86			input [`OR1200_W-1:0] X;
87			input [`OR1200_W-1:0] Y;
88			`input CLK;`
89			`input RST;`
90			output [`OR1200_WW-1:0] P;
91
92			reg [`OR1200_WW-1:0] p0;
93			reg [`OR1200_WW-1:0] p1;
94			`integer xi;`
95			`integer yi;`
96
97			`//`
98			`// Conversion unsigned to signed`
99			`//`
100			`always @(X)`
101			`xi <= X;`
102
103			`//`
104			`// Conversion unsigned to signed`
105			`//`
106			`always @(Y)`
107			`yi <= Y;`
108
109			`//`
110			`// First multiply stage`
111			`//`
112			`always @(posedge CLK or posedge RST)`
113			`if (RST)`
114			p0 <= `OR1200_WW'b0;
115			`else`
116			`p0 <= #1 xi * yi;`
117
118			`//`
119			`// Second multiply stage`
120			`//`
121			`always @(posedge CLK or posedge RST)`
122			`if (RST)`
123			p1 <= `OR1200_WW'b0;
124			`else`
125			`p1 <= #1 p0;`
126
127			`assign P = p1;`
128
129			`endmodule`
130
131			`endif

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_gmultp2_32x32.v] - Blame information for rev 55