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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_ram.v] - Blame information for rev 312

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1 10 unneback 
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's IC RAMs                                            ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of Instruction cache data rams                ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
46 141 marcus.erl 
// $Log: or1200_ic_ram.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// Minor update:
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// Coding style changed.
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//
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// Revision 1.6  2004/06/08 18:17:36  lampret
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// Non-functional changes. Coding style fixes.
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//
54 10 unneback 
// Revision 1.5  2004/04/08 11:00:46  simont
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// Add support for 512B instruction cache.
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//
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// Revision 1.4  2004/04/05 08:29:57  lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.2.4.1  2003/12/09 11:46:48  simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.2  2002/10/17 20:04:40  lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.9  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.8  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.3  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.2  2001/07/22 03:31:54  lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_ic_ram(
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        // Clock and reset
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        clk, rst,
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`ifdef OR1200_BIST
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        // RAM BIST
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        mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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        // Internal i/f
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        addr, en, we, datain, dataout
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_ICINDX;
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//
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// I/O
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//
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input                           clk;
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input                           rst;
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input   [aw-1:0]         addr;
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input                           en;
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input   [3:0]                    we;
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input   [dw-1:0]         datain;
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output  [dw-1:0]         dataout;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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`endif
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`ifdef OR1200_NO_IC
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//
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// Insn cache not implemented
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//
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assign dataout = {dw{1'b0}};
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`ifdef OR1200_BIST
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assign mbist_so_o = mbist_si_i;
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`endif
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`else
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//
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// Instantiation of IC RAM block
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//
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`ifdef OR1200_IC_1W_512B
146 141 marcus.erl 
   or1200_spram #
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     (
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      .aw(9),
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      .dw(32)
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      )
151 10 unneback 
`endif
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`ifdef OR1200_IC_1W_4KB
153 141 marcus.erl 
   or1200_spram #
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     (
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      .aw(10),
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      .dw(32)
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      )
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`endif
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`ifdef OR1200_IC_1W_8KB
160 141 marcus.erl 
   or1200_spram #
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     (
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      .aw(11),
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      .dw(32)
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      )
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`endif
166 141 marcus.erl 
   ic_ram0
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     (
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`ifdef OR1200_BIST
169 141 marcus.erl 
      // RAM BIST
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      .mbist_si_i(mbist_si_i),
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      .mbist_so_o(mbist_so_o),
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      .mbist_ctrl_i(mbist_ctrl_i),
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`endif
174 141 marcus.erl 
      .clk(clk),
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      .ce(en),
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      .we(we[0]),
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      //.oe(1'b1),
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      .addr(addr),
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      .di(datain),
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      .doq(dataout)
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      );
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`endif
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endmodule
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