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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_ram.v] - Blame information for rev 777

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's IC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of Instruction cache data rams                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_ic_ram.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Coding style changed.
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_ic_ram(
        // Clock and reset
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // Internal i/f
        addr, en, we, datain, dataout
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input   [3:0]                    we;
input   [dw-1:0]         datain;
output  [dw-1:0]         dataout;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
`ifdef OR1200_NO_IC
 
//
// Insn cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`else
 
//
// Instantiation of IC RAM block
//
   or1200_spram #
     (
      .aw(`OR1200_ICINDX),
      .dw(32)
      )
   ic_ram0
     (
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(mbist_si_i),
      .mbist_so_o(mbist_so_o),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
      .clk(clk),
      .ce(en),
      .we(we[0]),
      //.oe(1'b1),
      .addr(addr),
      .di(datain),
      .doq(dataout)
      );
`endif
 
endmodule
 

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's IC RAMs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of Instruction cache data rams ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	141	marcus.erl	`// $Log: or1200_ic_ram.v,v $`
47			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
48			`// Minor update:`
49			`// Coding style changed.`
50			`//`
51	10	unneback
52			`// synopsys translate_off`
53			`include "timescale.v"
54			`// synopsys translate_on`
55			`include "or1200_defines.v"
56
57			`module or1200_ic_ram(`
58			`// Clock and reset`
59			`clk, rst,`
60
61			`ifdef OR1200_BIST
62			`// RAM BIST`
63			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
64			`endif
65
66			`// Internal i/f`
67			`addr, en, we, datain, dataout`
68			`);`
69
70			parameter dw = `OR1200_OPERAND_WIDTH;
71			parameter aw = `OR1200_ICINDX;
72
73			`//`
74			`// I/O`
75			`//`
76			`input clk;`
77			`input rst;`
78			`input [aw-1:0] addr;`
79			`input en;`
80			`input [3:0] we;`
81			`input [dw-1:0] datain;`
82			`output [dw-1:0] dataout;`
83
84			`ifdef OR1200_BIST
85			`//`
86			`// RAM BIST`
87			`//`
88			`input mbist_si_i;`
89			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
90			`output mbist_so_o;`
91			`endif
92
93			`ifdef OR1200_NO_IC
94
95			`//`
96			`// Insn cache not implemented`
97			`//`
98			`assign dataout = {dw{1'b0}};`
99			`ifdef OR1200_BIST
100			`assign mbist_so_o = mbist_si_i;`
101			`endif
102
103			`else
104
105			`//`
106			`// Instantiation of IC RAM block`
107			`//`
108	141	marcus.erl	`or1200_spram #`
109			`(`
110	481	julius	.aw(`OR1200_ICINDX),
111	141	marcus.erl	`.dw(32)`
112			`)`
113			`ic_ram0`
114			`(`
115	10	unneback	`ifdef OR1200_BIST
116	141	marcus.erl	`// RAM BIST`
117			`.mbist_si_i(mbist_si_i),`
118			`.mbist_so_o(mbist_so_o),`
119			`.mbist_ctrl_i(mbist_ctrl_i),`
120	10	unneback	`endif
121	141	marcus.erl	`.clk(clk),`
122			`.ce(en),`
123			`.we(we[0]),`
124			`//.oe(1'b1),`
125			`.addr(addr),`
126			`.di(datain),`
127			`.doq(dataout)`
128			`);`
129	10	unneback	`endif
130
131			`endmodule`
132

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_ram.v] - Blame information for rev 777