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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_top.v] - Blame information for rev 588

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
3 481 julius
////  OR1200's Instruction Cache top level                        ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://opencores.org/project,or1k                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of all IC blocks.                             ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
44 141 marcus.erl
// $Log: or1200_ic_top.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// No update 
47 10 unneback
 
48
// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
52
 
53
//
54 481 julius
// Instruction cache top
55 10 unneback
//
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module or1200_ic_top(
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        // Rst, clk and clock control
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        clk, rst,
59
 
60
        // External i/f
61 481 julius
        icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o,
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        icbiu_sel_o, icbiu_cab_o, icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
63 10 unneback
 
64
        // Internal i/f
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        ic_en,
66 481 julius
        icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i, icqmem_sel_i, icqmem_tag_i,
67 10 unneback
        icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
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69
`ifdef OR1200_BIST
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        // RAM BIST
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        mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
73
 
74
        // SPRs
75
        spr_cs, spr_write, spr_dat_i
76
);
77
 
78
parameter dw = `OR1200_OPERAND_WIDTH;
79
 
80
//
81
// I/O
82
//
83
 
84
//
85
// Clock and reset
86
//
87
input                           clk;
88
input                           rst;
89
 
90
//
91
// External I/F
92
//
93
output  [dw-1:0]         icbiu_dat_o;
94
output  [31:0]                   icbiu_adr_o;
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output                          icbiu_cyc_o;
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output                          icbiu_stb_o;
97
output                          icbiu_we_o;
98
output  [3:0]                    icbiu_sel_o;
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output                          icbiu_cab_o;
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input   [dw-1:0]         icbiu_dat_i;
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input                           icbiu_ack_i;
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input                           icbiu_err_i;
103
 
104
//
105
// Internal I/F
106
//
107
input                           ic_en;
108
input   [31:0]                   icqmem_adr_i;
109
input                           icqmem_cycstb_i;
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input                           icqmem_ci_i;
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input   [3:0]                    icqmem_sel_i;
112
input   [3:0]                    icqmem_tag_i;
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output  [dw-1:0]         icqmem_dat_o;
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output                          icqmem_ack_o;
115
output                          icqmem_rty_o;
116
output                          icqmem_err_o;
117
output  [3:0]                    icqmem_tag_o;
118
 
119
`ifdef OR1200_BIST
120
//
121
// RAM BIST
122
//
123
input mbist_si_i;
124
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
125
output mbist_so_o;
126
`endif
127
 
128
//
129
// SPR access
130
//
131
input                           spr_cs;
132
input                           spr_write;
133
input   [31:0]                   spr_dat_i;
134
 
135
//
136
// Internal wires and regs
137
//
138
wire                            tag_v;
139
wire    [`OR1200_ICTAG_W-2:0]    tag;
140
wire    [dw-1:0]         to_icram;
141
wire    [dw-1:0]         from_icram;
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wire    [31:0]                   saved_addr;
143
wire    [3:0]                    icram_we;
144
wire                            ictag_we;
145
wire    [31:0]                   ic_addr;
146
wire                            icfsm_biu_read;
147 481 julius
/* verilator lint_off UNOPTFLAT */
148 10 unneback
reg                             tagcomp_miss;
149 481 julius
/* verilator lint_on UNOPTFLAT */
150 10 unneback
wire    [`OR1200_ICINDXH:`OR1200_ICLS]  ictag_addr;
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wire                            ictag_en;
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wire                            ictag_v;
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wire                            ic_inv;
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wire                            icfsm_first_hit_ack;
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wire                            icfsm_first_miss_ack;
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wire                            icfsm_first_miss_err;
157
wire                            icfsm_burst;
158
wire                            icfsm_tag_we;
159 481 julius
reg                             ic_inv_q;
160
 
161 10 unneback
`ifdef OR1200_BIST
162
//
163
// RAM BIST
164
//
165
wire                            mbist_ram_so;
166
wire                            mbist_tag_so;
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wire                            mbist_ram_si = mbist_si_i;
168
wire                            mbist_tag_si = mbist_ram_so;
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assign                          mbist_so_o = mbist_tag_so;
170
`endif
171
 
172
//
173
// Simple assignments
174
//
175
assign icbiu_adr_o = ic_addr;
176
assign ic_inv = spr_cs & spr_write;
177
assign ictag_we = icfsm_tag_we | ic_inv;
178 258 julius
assign ictag_addr = ic_inv ?
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                    spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] :
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                    ic_addr[`OR1200_ICINDXH:`OR1200_ICLS];
181 10 unneback
assign ictag_en = ic_inv | ic_en;
182
assign ictag_v = ~ic_inv;
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184
//
185
// Data to BIU is from ICRAM when IC is enabled or from LSU when
186
// IC is disabled
187
//
188
assign icbiu_dat_o = 32'h00000000;
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190
//
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// Bypases of the IC when IC is disabled
192
//
193
assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
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assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
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assign icbiu_we_o = 1'b0;
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assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icqmem_sel_i;
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assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
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assign icqmem_rty_o = ~icqmem_ack_o & ~icqmem_err_o;
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assign icqmem_tag_o = icqmem_err_o ? `OR1200_ITAG_BE : icqmem_tag_i;
200
 
201
//
202
// CPU normal and error termination
203
//
204
assign icqmem_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
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assign icqmem_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
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207
//
208
// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
209
//
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assign ic_addr = (icfsm_biu_read) ? saved_addr : icqmem_adr_i;
211
 
212
//
213
// Select between input data generated by LSU or by BIU
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//
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assign to_icram = icbiu_dat_i;
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217
//
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// Select between data generated by ICRAM or passed by BIU
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//
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assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
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222
//
223 481 julius
// Detect falling edge of IC invalidate signal
224
// 
225
always @(posedge clk or `OR1200_RST_EVENT rst)
226
   if (rst==`OR1200_RST_VALUE)
227
     ic_inv_q <= 1'b0;
228
   else
229
     ic_inv_q <= ic_inv;
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231
 
232
//
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// Tag comparison
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//
235 481 julius
// During line invalidate, ensure it stays the same
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always @(tag or saved_addr or tag_v) begin
237 481 julius
          if ((tag != saved_addr[31:`OR1200_ICTAGL]) | !tag_v)
238
            tagcomp_miss = 1'b1;
239
          else
240
            tagcomp_miss = 1'b0;
241 10 unneback
end
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243
//
244
// Instantiation of IC Finite State Machine
245
//
246
or1200_ic_fsm or1200_ic_fsm(
247
        .clk(clk),
248
        .rst(rst),
249
        .ic_en(ic_en),
250
        .icqmem_cycstb_i(icqmem_cycstb_i),
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        .icqmem_ci_i(icqmem_ci_i),
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        .tagcomp_miss(tagcomp_miss),
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        .biudata_valid(icbiu_ack_i),
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        .biudata_error(icbiu_err_i),
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        .start_addr(icqmem_adr_i),
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        .saved_addr(saved_addr),
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        .icram_we(icram_we),
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        .biu_read(icfsm_biu_read),
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        .first_hit_ack(icfsm_first_hit_ack),
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        .first_miss_ack(icfsm_first_miss_ack),
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        .first_miss_err(icfsm_first_miss_err),
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        .burst(icfsm_burst),
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        .tag_we(icfsm_tag_we)
264
);
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266
//
267
// Instantiation of IC main memory
268
//
269
or1200_ic_ram or1200_ic_ram(
270
        .clk(clk),
271
        .rst(rst),
272
`ifdef OR1200_BIST
273
        // RAM BIST
274
        .mbist_si_i(mbist_ram_si),
275
        .mbist_so_o(mbist_ram_so),
276
        .mbist_ctrl_i(mbist_ctrl_i),
277
`endif
278
        .addr(ic_addr[`OR1200_ICINDXH:2]),
279
        .en(ic_en),
280
        .we(icram_we),
281
        .datain(to_icram),
282
        .dataout(from_icram)
283
);
284
 
285
//
286
// Instantiation of IC TAG memory
287
//
288
or1200_ic_tag or1200_ic_tag(
289
        .clk(clk),
290
        .rst(rst),
291
`ifdef OR1200_BIST
292
        // RAM BIST
293
        .mbist_si_i(mbist_tag_si),
294
        .mbist_so_o(mbist_tag_so),
295
        .mbist_ctrl_i(mbist_ctrl_i),
296
`endif
297
        .addr(ictag_addr),
298
        .en(ictag_en),
299
        .we(ictag_we),
300
        .datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}),
301
        .tag_v(tag_v),
302
        .tag(tag)
303
);
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endmodule

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