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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_top.v] - Blame information for rev 156

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1 10 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Data Cache top level                               ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of all IC blocks.                             ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
46 141 marcus.erl
// $Log: or1200_ic_top.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// No update 
49
//
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// Revision 1.9  2004/04/05 08:29:57  lampret
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// Merged branch_qmem into main tree.
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//
53 10 unneback
// Revision 1.7.4.2  2003/12/09 11:46:48  simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.7  2002/10/17 20:04:40  lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.6  2002/03/29 15:16:55  lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5  2002/02/11 04:33:17  lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4  2002/02/01 19:56:54  lampret
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// Fixed combinational loops.
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//
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// Revision 1.3  2002/01/28 01:16:00  lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
73
//
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// Revision 1.2  2002/01/14 06:18:22  lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.9  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
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// no message
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//
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// Revision 1.4  2001/08/13 03:36:20  lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.3  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.2  2001/07/22 03:31:53  lampret
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// Fixed RAM's oen bug. Cache bypass under development.
97
//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
101
//
102
 
103
// synopsys translate_off
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`include "timescale.v"
105
// synopsys translate_on
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`include "or1200_defines.v"
107
 
108
//
109
// Data cache
110
//
111
module or1200_ic_top(
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        // Rst, clk and clock control
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        clk, rst,
114
 
115
        // External i/f
116
        icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
117
        icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
118
 
119
        // Internal i/f
120
        ic_en,
121
        icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i,
122
        icqmem_sel_i, icqmem_tag_i,
123
        icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
124
 
125
`ifdef OR1200_BIST
126
        // RAM BIST
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        mbist_si_i, mbist_so_o, mbist_ctrl_i,
128
`endif
129
 
130
        // SPRs
131
        spr_cs, spr_write, spr_dat_i
132
);
133
 
134
parameter dw = `OR1200_OPERAND_WIDTH;
135
 
136
//
137
// I/O
138
//
139
 
140
//
141
// Clock and reset
142
//
143
input                           clk;
144
input                           rst;
145
 
146
//
147
// External I/F
148
//
149
output  [dw-1:0]         icbiu_dat_o;
150
output  [31:0]                   icbiu_adr_o;
151
output                          icbiu_cyc_o;
152
output                          icbiu_stb_o;
153
output                          icbiu_we_o;
154
output  [3:0]                    icbiu_sel_o;
155
output                          icbiu_cab_o;
156
input   [dw-1:0]         icbiu_dat_i;
157
input                           icbiu_ack_i;
158
input                           icbiu_err_i;
159
 
160
//
161
// Internal I/F
162
//
163
input                           ic_en;
164
input   [31:0]                   icqmem_adr_i;
165
input                           icqmem_cycstb_i;
166
input                           icqmem_ci_i;
167
input   [3:0]                    icqmem_sel_i;
168
input   [3:0]                    icqmem_tag_i;
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output  [dw-1:0]         icqmem_dat_o;
170
output                          icqmem_ack_o;
171
output                          icqmem_rty_o;
172
output                          icqmem_err_o;
173
output  [3:0]                    icqmem_tag_o;
174
 
175
`ifdef OR1200_BIST
176
//
177
// RAM BIST
178
//
179
input mbist_si_i;
180
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
181
output mbist_so_o;
182
`endif
183
 
184
//
185
// SPR access
186
//
187
input                           spr_cs;
188
input                           spr_write;
189
input   [31:0]                   spr_dat_i;
190
 
191
//
192
// Internal wires and regs
193
//
194
wire                            tag_v;
195
wire    [`OR1200_ICTAG_W-2:0]    tag;
196
wire    [dw-1:0]         to_icram;
197
wire    [dw-1:0]         from_icram;
198
wire    [31:0]                   saved_addr;
199
wire    [3:0]                    icram_we;
200
wire                            ictag_we;
201
wire    [31:0]                   ic_addr;
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wire                            icfsm_biu_read;
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reg                             tagcomp_miss;
204
wire    [`OR1200_ICINDXH:`OR1200_ICLS]  ictag_addr;
205
wire                            ictag_en;
206
wire                            ictag_v;
207
wire                            ic_inv;
208
wire                            icfsm_first_hit_ack;
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wire                            icfsm_first_miss_ack;
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wire                            icfsm_first_miss_err;
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wire                            icfsm_burst;
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wire                            icfsm_tag_we;
213
`ifdef OR1200_BIST
214
//
215
// RAM BIST
216
//
217
wire                            mbist_ram_so;
218
wire                            mbist_tag_so;
219
wire                            mbist_ram_si = mbist_si_i;
220
wire                            mbist_tag_si = mbist_ram_so;
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assign                          mbist_so_o = mbist_tag_so;
222
`endif
223
 
224
//
225
// Simple assignments
226
//
227
assign icbiu_adr_o = ic_addr;
228
assign ic_inv = spr_cs & spr_write;
229
assign ictag_we = icfsm_tag_we | ic_inv;
230
assign ictag_addr = ic_inv ? spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] : ic_addr[`OR1200_ICINDXH:`OR1200_ICLS];
231
assign ictag_en = ic_inv | ic_en;
232
assign ictag_v = ~ic_inv;
233
 
234
//
235
// Data to BIU is from ICRAM when IC is enabled or from LSU when
236
// IC is disabled
237
//
238
assign icbiu_dat_o = 32'h00000000;
239
 
240
//
241
// Bypases of the IC when IC is disabled
242
//
243
assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
244
assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
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assign icbiu_we_o = 1'b0;
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assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icqmem_sel_i;
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assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
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assign icqmem_rty_o = ~icqmem_ack_o & ~icqmem_err_o;
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assign icqmem_tag_o = icqmem_err_o ? `OR1200_ITAG_BE : icqmem_tag_i;
250
 
251
//
252
// CPU normal and error termination
253
//
254
assign icqmem_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
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assign icqmem_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
256
 
257
//
258
// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
259
//
260
assign ic_addr = (icfsm_biu_read) ? saved_addr : icqmem_adr_i;
261
 
262
//
263
// Select between input data generated by LSU or by BIU
264
//
265
assign to_icram = icbiu_dat_i;
266
 
267
//
268
// Select between data generated by ICRAM or passed by BIU
269
//
270
assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
271
 
272
//
273
// Tag comparison
274
//
275
always @(tag or saved_addr or tag_v) begin
276
        if ((tag != saved_addr[31:`OR1200_ICTAGL]) || !tag_v)
277
                tagcomp_miss = 1'b1;
278
        else
279
                tagcomp_miss = 1'b0;
280
end
281
 
282
//
283
// Instantiation of IC Finite State Machine
284
//
285
or1200_ic_fsm or1200_ic_fsm(
286
        .clk(clk),
287
        .rst(rst),
288
        .ic_en(ic_en),
289
        .icqmem_cycstb_i(icqmem_cycstb_i),
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        .icqmem_ci_i(icqmem_ci_i),
291
        .tagcomp_miss(tagcomp_miss),
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        .biudata_valid(icbiu_ack_i),
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        .biudata_error(icbiu_err_i),
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        .start_addr(icqmem_adr_i),
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        .saved_addr(saved_addr),
296
        .icram_we(icram_we),
297
        .biu_read(icfsm_biu_read),
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        .first_hit_ack(icfsm_first_hit_ack),
299
        .first_miss_ack(icfsm_first_miss_ack),
300
        .first_miss_err(icfsm_first_miss_err),
301
        .burst(icfsm_burst),
302
        .tag_we(icfsm_tag_we)
303
);
304
 
305
//
306
// Instantiation of IC main memory
307
//
308
or1200_ic_ram or1200_ic_ram(
309
        .clk(clk),
310
        .rst(rst),
311
`ifdef OR1200_BIST
312
        // RAM BIST
313
        .mbist_si_i(mbist_ram_si),
314
        .mbist_so_o(mbist_ram_so),
315
        .mbist_ctrl_i(mbist_ctrl_i),
316
`endif
317
        .addr(ic_addr[`OR1200_ICINDXH:2]),
318
        .en(ic_en),
319
        .we(icram_we),
320
        .datain(to_icram),
321
        .dataout(from_icram)
322
);
323
 
324
//
325
// Instantiation of IC TAG memory
326
//
327
or1200_ic_tag or1200_ic_tag(
328
        .clk(clk),
329
        .rst(rst),
330
`ifdef OR1200_BIST
331
        // RAM BIST
332
        .mbist_si_i(mbist_tag_si),
333
        .mbist_so_o(mbist_tag_so),
334
        .mbist_ctrl_i(mbist_ctrl_i),
335
`endif
336
        .addr(ictag_addr),
337
        .en(ictag_en),
338
        .we(ictag_we),
339
        .datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}),
340
        .tag_v(tag_v),
341
        .tag(tag)
342
);
343
 
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endmodule

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