URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_if.v] - Blame information for rev 141

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's instruction fetch                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, instruction fetch, interface to IC.                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_if.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Structure reordered and bugs fixed. 
//
// Revision 1.5  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.2  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_if(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
 
        // Internal i/f
        if_freeze, if_insn, if_pc, if_flushpipe, saving_if_insn,
        if_stall, no_more_dslot, genpc_refetch, rfe,
        except_itlbmiss, except_immufault, except_ibuserr
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
input   [31:0]                   icpu_dat_i;
input                           icpu_ack_i;
input                           icpu_err_i;
input   [31:0]                   icpu_adr_i;
input   [3:0]                    icpu_tag_i;
 
//
// Internal i/f
//
input                           if_freeze;
output  [31:0]                   if_insn;
output  [31:0]                   if_pc;
input                           if_flushpipe;
output                          saving_if_insn;
output                          if_stall;
input                           no_more_dslot;
output                          genpc_refetch;
input                           rfe;
output                          except_itlbmiss;
output                          except_immufault;
output                          except_ibuserr;
 
//
// Internal wires and regs
//
wire                    save_insn;
wire                    if_bypass;
reg                     if_bypass_reg;
reg     [31:0]           insn_saved;
reg     [31:0]           addr_saved;
reg     [2:0]            err_saved;
reg                     saved;
 
assign save_insn = (icpu_ack_i | icpu_err_i) & if_freeze & !saved;
assign saving_if_insn = !if_flushpipe & save_insn;
 
//
// IF bypass 
//
assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe;
 
always @(posedge clk or posedge rst)
        if (rst)
                if_bypass_reg <= #1 1'b0;
        else
                if_bypass_reg <= #1 if_bypass;
 
//
// IF stage insn
//
assign if_insn = no_more_dslot | rfe | if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
assign if_pc = saved ? addr_saved : {icpu_adr_i[31:2], 2'h0};
assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
assign genpc_refetch = saved & icpu_ack_i;
assign except_itlbmiss = no_more_dslot ? 1'b0 : saved ? err_saved[0] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
assign except_immufault = no_more_dslot ? 1'b0 : saved ? err_saved[1] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
assign except_ibuserr = no_more_dslot ? 1'b0 : saved ? err_saved[2] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
 
//
// Flag for saved insn/address
//
always @(posedge clk or posedge rst)
        if (rst)
                saved <= #1 1'b0;
        else if (if_flushpipe)
                saved <= #1 1'b0;
        else if (save_insn)
                saved <= #1 1'b1;
        else if (!if_freeze)
                saved <= #1 1'b0;
 
//
// Store fetched instruction
//
always @(posedge clk or posedge rst)
        if (rst)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
        else if (if_flushpipe)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
        else if (save_insn)
                insn_saved <= #1 icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
        else if (!if_freeze)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
 
//
// Store fetched instruction's address
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_saved <= #1 32'h00000000;
        else if (if_flushpipe)
                addr_saved <= #1 32'h00000000;
        else if (save_insn)
                addr_saved <= #1 {icpu_adr_i[31:2], 2'b00};
        else if (!if_freeze)
                addr_saved <= #1 {icpu_adr_i[31:2], 2'b00};
 
//
// Store fetched instruction's error tags 
//
always @(posedge clk or posedge rst)
        if (rst)
                err_saved <= #1 3'b000;
        else if (if_flushpipe)
                err_saved <= #1 3'b000;
        else if (save_insn) begin
                err_saved[0] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
                err_saved[1] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
                err_saved[2] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
        end
        else if (!if_freeze)
                err_saved <= #1 3'b000;
 
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's instruction fetch ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PC, instruction fetch, interface to IC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	141	marcus.erl	`// $Log: or1200_if.v,v $`
47			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
48			`// Major update:`
49			`// Structure reordered and bugs fixed.`
50			`//`
51			`// Revision 1.5 2004/04/05 08:29:57 lampret`
52			`// Merged branch_qmem into main tree.`
53			`//`
54	10	unneback	`// Revision 1.3 2002/03/29 15:16:56 lampret`
55			`// Some of the warnings fixed.`
56			`//`
57			`// Revision 1.2 2002/01/28 01:16:00 lampret`
58			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
59			`//`
60			`// Revision 1.1 2002/01/03 08:16:15 lampret`
61			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
62			`//`
63			`// Revision 1.10 2001/11/20 18:46:15 simons`
64			`// Break point bug fixed`
65			`//`
66			`// Revision 1.9 2001/11/18 09:58:28 lampret`
67			`// Fixed some l.trap typos.`
68			`//`
69			`// Revision 1.8 2001/11/18 08:36:28 lampret`
70			`// For GDB changed single stepping and disabled trap exception.`
71			`//`
72			`// Revision 1.7 2001/10/21 17:57:16 lampret`
73			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
74			`//`
75			`// Revision 1.6 2001/10/14 13:12:09 lampret`
76			`// MP3 version.`
77			`//`
78			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
79			`// no message`
80			`//`
81			`// Revision 1.1 2001/08/09 13:39:33 lampret`
82			`// Major clean-up.`
83			`//`
84			`//`
85
86			`// synopsys translate_off`
87			`include "timescale.v"
88			`// synopsys translate_on`
89			`include "or1200_defines.v"
90
91			`module or1200_if(`
92			`// Clock and reset`
93			`clk, rst,`
94
95			`// External i/f to IC`
96			`icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,`
97
98			`// Internal i/f`
99	141	marcus.erl	`if_freeze, if_insn, if_pc, if_flushpipe, saving_if_insn,`
100	10	unneback	`if_stall, no_more_dslot, genpc_refetch, rfe,`
101			`except_itlbmiss, except_immufault, except_ibuserr`
102			`);`
103
104			`//`
105			`// I/O`
106			`//`
107
108			`//`
109			`// Clock and reset`
110			`//`
111			`input clk;`
112			`input rst;`
113
114			`//`
115			`// External i/f to IC`
116			`//`
117			`input [31:0] icpu_dat_i;`
118			`input icpu_ack_i;`
119			`input icpu_err_i;`
120			`input [31:0] icpu_adr_i;`
121			`input [3:0] icpu_tag_i;`
122
123			`//`
124			`// Internal i/f`
125			`//`
126			`input if_freeze;`
127			`output [31:0] if_insn;`
128			`output [31:0] if_pc;`
129	141	marcus.erl	`input if_flushpipe;`
130			`output saving_if_insn;`
131	10	unneback	`output if_stall;`
132			`input no_more_dslot;`
133			`output genpc_refetch;`
134			`input rfe;`
135			`output except_itlbmiss;`
136			`output except_immufault;`
137			`output except_ibuserr;`
138
139			`//`
140			`// Internal wires and regs`
141			`//`
142	141	marcus.erl	`wire save_insn;`
143			`wire if_bypass;`
144			`reg if_bypass_reg;`
145			`reg [31:0] insn_saved;`
146			`reg [31:0] addr_saved;`
147			`reg [2:0] err_saved;`
148			`reg saved;`
149	10	unneback
150	141	marcus.erl	`assign save_insn = (icpu_ack_i \| icpu_err_i) & if_freeze & !saved;`
151			`assign saving_if_insn = !if_flushpipe & save_insn;`
152
153	10	unneback	`//`
154	141	marcus.erl	`// IF bypass`
155			`//`
156			`assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg \| if_flushpipe;`
157
158			`always @(posedge clk or posedge rst)`
159			`if (rst)`
160			`if_bypass_reg <= #1 1'b0;`
161			`else`
162			`if_bypass_reg <= #1 if_bypass;`
163
164			`//`
165	10	unneback	`// IF stage insn`
166			`//`
167	141	marcus.erl	assign if_insn = no_more_dslot \| rfe \| if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
168			`assign if_pc = saved ? addr_saved : {icpu_adr_i[31:2], 2'h0};`
169	10	unneback	`assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;`
170			`assign genpc_refetch = saved & icpu_ack_i;`
171	141	marcus.erl	assign except_itlbmiss = no_more_dslot ? 1'b0 : saved ? err_saved[0] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
172			assign except_immufault = no_more_dslot ? 1'b0 : saved ? err_saved[1] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
173			assign except_ibuserr = no_more_dslot ? 1'b0 : saved ? err_saved[2] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
174	10	unneback
175			`//`
176			`// Flag for saved insn/address`
177			`//`
178			`always @(posedge clk or posedge rst)`
179			`if (rst)`
180			`saved <= #1 1'b0;`
181	141	marcus.erl	`else if (if_flushpipe)`
182	10	unneback	`saved <= #1 1'b0;`
183	141	marcus.erl	`else if (save_insn)`
184	10	unneback	`saved <= #1 1'b1;`
185			`else if (!if_freeze)`
186			`saved <= #1 1'b0;`
187
188			`//`
189			`// Store fetched instruction`
190			`//`
191			`always @(posedge clk or posedge rst)`
192			`if (rst)`
193			insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
194	141	marcus.erl	`else if (if_flushpipe)`
195	10	unneback	insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
196	141	marcus.erl	`else if (save_insn)`
197			insn_saved <= #1 icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
198	10	unneback	`else if (!if_freeze)`
199			insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
200
201			`//`
202			`// Store fetched instruction's address`
203			`//`
204			`always @(posedge clk or posedge rst)`
205			`if (rst)`
206			`addr_saved <= #1 32'h00000000;`
207	141	marcus.erl	`else if (if_flushpipe)`
208	10	unneback	`addr_saved <= #1 32'h00000000;`
209	141	marcus.erl	`else if (save_insn)`
210			`addr_saved <= #1 {icpu_adr_i[31:2], 2'b00};`
211	10	unneback	`else if (!if_freeze)`
212	141	marcus.erl	`addr_saved <= #1 {icpu_adr_i[31:2], 2'b00};`
213	10	unneback
214	141	marcus.erl	`//`
215			`// Store fetched instruction's error tags`
216			`//`
217			`always @(posedge clk or posedge rst)`
218			`if (rst)`
219			`err_saved <= #1 3'b000;`
220			`else if (if_flushpipe)`
221			`err_saved <= #1 3'b000;`
222			`else if (save_insn) begin`
223			err_saved[0] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
224			err_saved[1] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
225			err_saved[2] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
226			`end`
227			`else if (!if_freeze)`
228			`err_saved <= #1 3'b000;`
229
230
231	10	unneback	`endmodule`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_if.v] - Blame information for rev 141