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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's instruction fetch ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// PC, instruction fetch, interface to IC. ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.2 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10 2001/11/20 18:46:15 simons
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// Break point bug fixed
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//
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// Revision 1.9 2001/11/18 09:58:28 lampret
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// Fixed some l.trap typos.
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//
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// Revision 1.8 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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//
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// Revision 1.7 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.6 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.1 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_if(
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// Clock and reset
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clk, rst,
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// External i/f to IC
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icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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// Internal i/f
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if_freeze, if_insn, if_pc, flushpipe,
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if_stall, no_more_dslot, genpc_refetch, rfe,
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except_itlbmiss, except_immufault, except_ibuserr
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);
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input clk;
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input rst;
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//
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// External i/f to IC
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//
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input [31:0] icpu_dat_i;
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input icpu_ack_i;
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input icpu_err_i;
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input [31:0] icpu_adr_i;
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input [3:0] icpu_tag_i;
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//
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// Internal i/f
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//
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input if_freeze;
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output [31:0] if_insn;
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output [31:0] if_pc;
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input flushpipe;
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output if_stall;
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input no_more_dslot;
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output genpc_refetch;
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input rfe;
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output except_itlbmiss;
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output except_immufault;
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output except_ibuserr;
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//
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// Internal wires and regs
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//
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reg [31:0] insn_saved;
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reg [31:0] addr_saved;
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reg saved;
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//
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// IF stage insn
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//
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assign if_insn = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
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assign if_pc = saved ? addr_saved : icpu_adr_i;
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// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;
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assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
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assign genpc_refetch = saved & icpu_ack_i;
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assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot;
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assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot;
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assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot;
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//
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// Flag for saved insn/address
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//
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always @(posedge clk or posedge rst)
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if (rst)
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saved <= #1 1'b0;
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else if (flushpipe)
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saved <= #1 1'b0;
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else if (icpu_ack_i & if_freeze & !saved)
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saved <= #1 1'b1;
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else if (!if_freeze)
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saved <= #1 1'b0;
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//
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// Store fetched instruction
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//
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always @(posedge clk or posedge rst)
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if (rst)
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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else if (flushpipe)
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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else if (icpu_ack_i & if_freeze & !saved)
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insn_saved <= #1 icpu_dat_i;
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else if (!if_freeze)
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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//
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// Store fetched instruction's address
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//
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always @(posedge clk or posedge rst)
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if (rst)
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addr_saved <= #1 32'h00000000;
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else if (flushpipe)
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addr_saved <= #1 32'h00000000;
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else if (icpu_ack_i & if_freeze & !saved)
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addr_saved <= #1 icpu_adr_i;
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else if (!if_freeze)
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addr_saved <= #1 icpu_adr_i;
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endmodule
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