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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_immu_top.v] - Blame information for rev 679

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Instruction MMU top level                          ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
6 481 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
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////  Description                                                 ////
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////  Instantiation of all IMMU blocks.                           ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - cache inhibit                                            ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
43
 
44
// synopsys translate_off
45
`include "timescale.v"
46
// synopsys translate_on
47
`include "or1200_defines.v"
48
 
49
//
50
// Insn MMU
51
//
52
 
53
module or1200_immu_top(
54
        // Rst and clk
55
        clk, rst,
56
 
57
        // CPU i/f
58
        ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
59
        icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
60
 
61 141 marcus.erl
        // SR Interface
62
        boot_adr_sel_i,
63
 
64 10 unneback
        // SPR access
65
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
66
 
67
`ifdef OR1200_BIST
68
        // RAM BIST
69
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
70
`endif
71
 
72
        // QMEM i/f
73
        qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
74
);
75
 
76
parameter dw = `OR1200_OPERAND_WIDTH;
77
parameter aw = `OR1200_OPERAND_WIDTH;
78 679 olof
parameter boot_adr = `OR1200_BOOT_ADR;
79 10 unneback
 
80
//
81
// I/O
82
//
83
 
84
//
85
// Clock and reset
86
//
87
input                           clk;
88
input                           rst;
89
 
90
//
91
// CPU I/F
92
//
93
input                           ic_en;
94
input                           immu_en;
95
input                           supv;
96
input   [aw-1:0]         icpu_adr_i;
97
input                           icpu_cycstb_i;
98
output  [aw-1:0]         icpu_adr_o;
99
output  [3:0]                    icpu_tag_o;
100
output                          icpu_rty_o;
101
output                          icpu_err_o;
102
 
103
//
104 141 marcus.erl
// SR Interface
105
//
106
input                           boot_adr_sel_i;
107
 
108
//
109 10 unneback
// SPR access
110
//
111
input                           spr_cs;
112
input                           spr_write;
113
input   [aw-1:0]         spr_addr;
114
input   [31:0]                   spr_dat_i;
115
output  [31:0]                   spr_dat_o;
116
 
117
`ifdef OR1200_BIST
118
//
119
// RAM BIST
120
//
121
input mbist_si_i;
122
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
123
output mbist_so_o;
124
`endif
125
 
126
//
127
// IC I/F
128
//
129
input                           qmemimmu_rty_i;
130
input                           qmemimmu_err_i;
131
input   [3:0]                    qmemimmu_tag_i;
132
output  [aw-1:0]         qmemimmu_adr_o;
133
output                          qmemimmu_cycstb_o;
134
output                          qmemimmu_ci_o;
135
 
136
//
137
// Internal wires and regs
138
//
139
wire                            itlb_spr_access;
140
wire    [31:`OR1200_IMMU_PS]    itlb_ppn;
141
wire                            itlb_hit;
142
wire                            itlb_uxe;
143
wire                            itlb_sxe;
144
wire    [31:0]                   itlb_dat_o;
145
wire                            itlb_en;
146
wire                            itlb_ci;
147
wire                            itlb_done;
148
wire                            fault;
149
wire                            miss;
150
wire                            page_cross;
151 141 marcus.erl
reg     [31:0]                   icpu_adr_default;
152
reg                             icpu_adr_select;
153
reg             [31:0]           icpu_adr_o;
154 10 unneback
reg     [31:`OR1200_IMMU_PS]    icpu_vpn_r;
155
`ifdef OR1200_NO_IMMU
156
`else
157
reg                             itlb_en_r;
158 141 marcus.erl
reg                             dis_spr_access_frst_clk;
159
reg                             dis_spr_access_scnd_clk;
160 10 unneback
`endif
161
 
162
//
163
// Implemented bits inside match and translate registers
164
//
165
// itlbwYmrX: vpn 31-10  v 0
166
// itlbwYtrX: ppn 31-10  uxe 7  sxe 6
167
//
168
// itlb memory width:
169
// 19 bits for ppn
170
// 13 bits for vpn
171
// 1 bit for valid
172
// 2 bits for protection
173
// 1 bit for cache inhibit
174
 
175
//
176
// icpu_adr_o
177
//
178
`ifdef OR1200_REGISTERED_OUTPUTS
179 679 olof
wire    [31:0]                   icpu_adr_boot = boot_adr;
180
 
181 358 julius
always @(`OR1200_RST_EVENT rst or posedge clk)
182 141 marcus.erl
        // default value 
183 358 julius
        if (rst == `OR1200_RST_VALUE) begin
184 481 julius
                // select async. value due to reset state
185 258 julius
                icpu_adr_default <=  32'h0000_0100;
186 481 julius
                icpu_adr_select  <=  1'b1;
187 141 marcus.erl
        end
188 481 julius
        // selected value (different from default) is written 
189
        // into FF after reset state
190 141 marcus.erl
        else if (icpu_adr_select) begin
191 481 julius
                // dynamic value can only be assigned to FF out of reset!
192
                icpu_adr_default <=  icpu_adr_boot;
193
                // select FF value 
194
                icpu_adr_select  <=  1'b0;
195 141 marcus.erl
        end
196
        else begin
197 258 julius
                icpu_adr_default <=  icpu_adr_i;
198 141 marcus.erl
        end
199
 
200 481 julius
// select async. value for boot address after reset - PC jumps to the address 
201
// selected after boot! 
202
   //assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P : 
203
   // `OR1200_EXCEPT_EPH0_P), 12'h100} ;
204 141 marcus.erl
 
205
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
206
        if (icpu_adr_select)
207 481 julius
                // async. value is selected due to reset state 
208
                icpu_adr_o = icpu_adr_boot ;
209 10 unneback
        else
210 481 julius
                // FF value is selected 2nd clock after reset state 
211
                icpu_adr_o = icpu_adr_default ;
212 10 unneback
`else
213
Unsupported !!!
214
`endif
215
 
216
//
217
// Page cross
218
//
219
// Asserted when CPU address crosses page boundary. Most of the time it is zero.
220
//
221
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
222
 
223
//
224
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
225
// one clock cycle after offset part.
226
//
227 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
228
        if (rst == `OR1200_RST_VALUE)
229 258 julius
                icpu_vpn_r <=  {32-`OR1200_IMMU_PS{1'b0}};
230 10 unneback
        else
231 258 julius
                icpu_vpn_r <=  icpu_adr_i[31:`OR1200_IMMU_PS];
232 10 unneback
 
233
`ifdef OR1200_NO_IMMU
234
 
235
//
236
// Put all outputs in inactive state
237
//
238
assign spr_dat_o = 32'h00000000;
239
assign qmemimmu_adr_o = icpu_adr_i;
240
assign icpu_tag_o = qmemimmu_tag_i;
241
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
242
assign icpu_rty_o = qmemimmu_rty_i;
243
assign icpu_err_o = qmemimmu_err_i;
244
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
245
`ifdef OR1200_BIST
246
assign mbist_so_o = mbist_si_i;
247
`endif
248
`else
249
 
250
//
251
// ITLB SPR access
252
//
253
// 1200 - 12FF  itlbmr w0
254
// 1200 - 123F  itlbmr w0 [63:0]
255
//
256
// 1300 - 13FF  itlbtr w0
257
// 1300 - 133F  itlbtr w0 [63:0]
258
//
259 141 marcus.erl
assign itlb_spr_access = spr_cs & ~dis_spr_access_scnd_clk;
260 10 unneback
 
261
//
262
// Disable ITLB SPR access
263
//
264 141 marcus.erl
// This flops are used to mask ITLB miss/fault exception
265
// during first & second clock cycles of accessing ITLB SPR. In
266 10 unneback
// subsequent clock cycles it is assumed that ITLB SPR
267
// access was accomplished and that normal instruction fetching
268
// can proceed.
269
//
270 141 marcus.erl
// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
271
// dis_spr_access_frst_clk  sets dis_spr_access_scnd_clk and 
272
// icpu_rty_o clears it.
273 10 unneback
//
274 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
275
        if (rst == `OR1200_RST_VALUE)
276 258 julius
                dis_spr_access_frst_clk  <=  1'b0;
277 10 unneback
        else if (!icpu_rty_o)
278 258 julius
                dis_spr_access_frst_clk  <=  1'b0;
279 10 unneback
        else if (spr_cs)
280 258 julius
                dis_spr_access_frst_clk  <=  1'b1;
281 10 unneback
 
282 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
283
        if (rst == `OR1200_RST_VALUE)
284 258 julius
                dis_spr_access_scnd_clk  <=  1'b0;
285 141 marcus.erl
        else if (!icpu_rty_o)
286 258 julius
                dis_spr_access_scnd_clk  <=  1'b0;
287 141 marcus.erl
        else if (dis_spr_access_frst_clk)
288 258 julius
                dis_spr_access_scnd_clk  <=  1'b1;
289 141 marcus.erl
 
290 10 unneback
//
291
// Tags:
292
//
293 141 marcus.erl
// OR1200_ITAG_TE - TLB miss Exception
294
// OR1200_ITAG_PE - Page fault Exception
295 10 unneback
//
296 141 marcus.erl
assign icpu_tag_o = miss ? `OR1200_ITAG_TE : fault ? `OR1200_ITAG_PE : qmemimmu_tag_i;
297 10 unneback
 
298
//
299
// icpu_rty_o
300
//
301
// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
302 141 marcus.erl
//assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
303
assign icpu_rty_o = qmemimmu_rty_i;
304 10 unneback
 
305
//
306
// icpu_err_o
307
//
308
assign icpu_err_o = miss | fault | qmemimmu_err_i;
309
 
310
//
311
// Assert itlb_en_r after one clock cycle and when there is no
312
// ITLB SPR access
313
//
314 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
315
        if (rst == `OR1200_RST_VALUE)
316 258 julius
                itlb_en_r <=  1'b0;
317 10 unneback
        else
318 258 julius
                itlb_en_r <=  itlb_en & ~itlb_spr_access;
319 10 unneback
 
320
//
321
// ITLB lookup successful
322
//
323
assign itlb_done = itlb_en_r & ~page_cross;
324
 
325
//
326 141 marcus.erl
// Cut transfer when access (mtspr/mfspr) to/from ITLB occure or if something goes 
327
// wrong with translation. If IC is disabled, use delayed signals.
328 10 unneback
//
329
// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
330 141 marcus.erl
//assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
331
assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done & ~itlb_spr_access : icpu_cycstb_i & ~page_cross;
332 10 unneback
 
333
//
334
// Cache Inhibit
335
//
336
// Cache inhibit is not really needed for instruction memory subsystem.
337
// If we would doq it, we would doq it like this.
338
// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
339 141 marcus.erl
// However this causes an async combinatorial loop so we stick to
340 10 unneback
// no cache inhibit.
341 141 marcus.erl
//assign qmemimmu_ci_o = `OR1200_IMMU_CI;
342
// Cache inhibit without an async combinatorial loop 
343
assign qmemimmu_ci_o = immu_en ? itlb_ci : `OR1200_IMMU_CI;
344 10 unneback
 
345
 
346
//
347
// Physical address is either translated virtual address or
348
// simply equal when IMMU is disabled
349
//
350 141 marcus.erl
//assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
351
assign qmemimmu_adr_o = immu_en & itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0};
352 10 unneback
 
353 141 marcus.erl
reg     [31:0]                  spr_dat_reg;
354 10 unneback
//
355
// Output to SPRS unit
356
//
357 141 marcus.erl
// spr_dat_o is registered on the 1st clock of spr read 
358
// so itlb can continue with process during execution of mfspr.
359 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
360
        if (rst == `OR1200_RST_VALUE)
361 258 julius
                spr_dat_reg <=  32'h0000_0000;
362 141 marcus.erl
        else if (spr_cs & !dis_spr_access_scnd_clk)
363 258 julius
                spr_dat_reg <=  itlb_dat_o;
364 10 unneback
 
365 141 marcus.erl
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
366
 
367 10 unneback
//
368
// Page fault exception logic
369
//
370
assign fault = itlb_done &
371
                        (  (!supv & !itlb_uxe)          // Execute in user mode not enabled
372
                        || (supv & !itlb_sxe));         // Execute in supv mode not enabled
373
 
374
//
375
// TLB Miss exception logic
376
//
377
assign miss = itlb_done & !itlb_hit;
378
 
379
//
380
// ITLB Enable
381
//
382
assign itlb_en = immu_en & icpu_cycstb_i;
383
 
384
//
385
// Instantiation of ITLB
386
//
387
or1200_immu_tlb or1200_immu_tlb(
388
        // Rst and clk
389
        .clk(clk),
390
        .rst(rst),
391
 
392
        // I/F for translation
393
        .tlb_en(itlb_en),
394
        .vaddr(icpu_adr_i),
395
        .hit(itlb_hit),
396
        .ppn(itlb_ppn),
397
        .uxe(itlb_uxe),
398
        .sxe(itlb_sxe),
399
        .ci(itlb_ci),
400
 
401
`ifdef OR1200_BIST
402
        // RAM BIST
403
        .mbist_si_i(mbist_si_i),
404
        .mbist_so_o(mbist_so_o),
405
        .mbist_ctrl_i(mbist_ctrl_i),
406
`endif
407
 
408
        // SPR access
409
        .spr_cs(itlb_spr_access),
410
        .spr_write(spr_write),
411
        .spr_addr(spr_addr),
412
        .spr_dat_i(spr_dat_i),
413
        .spr_dat_o(itlb_dat_o)
414
);
415
 
416
`endif
417
 
418
endmodule

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