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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's WISHBONE BIU ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Implements WISHBONE interface ////
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//// ////
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//// To Do: ////
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//// - if biu_cyc/stb are deasserted and wb_ack_i is asserted ////
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//// and this happens even before aborted_r is asssrted, ////
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//// wb_ack_i will be delivered even though transfer is ////
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//// internally considered already aborted. However most ////
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//// wb_ack_i are externally registered and delayed. Normally ////
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//// this shouldn't cause any problems. ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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marcus.erl |
// $Log: or1200_iwb_biu.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// This module is obsolete.
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//
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// Revision 1.2 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.1 2003/12/05 00:12:08 lampret
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// New wb_biu for iwb interface.
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//
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// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.6 2003/04/07 20:57:46 lampret
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// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
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//
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// Revision 1.5 2002/12/08 08:57:56 lampret
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// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
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//
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// Revision 1.4 2002/09/16 03:09:16 lampret
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// Fixed a combinational loop.
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//
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// Revision 1.3 2002/08/12 05:31:37 lampret
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// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
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//
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// Revision 1.2 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.12 2001/11/22 13:42:51 lampret
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// Added wb_cyc_o assignment after it was removed by accident.
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//
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// Revision 1.11 2001/11/20 21:28:10 lampret
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// Added optional sampling of inputs.
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//
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// Revision 1.10 2001/11/18 11:32:00 lampret
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// OR1200_REGISTERED_OUTPUTS can now be enabled.
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.8 2001/10/14 13:12:10 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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//
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:23 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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marcus.erl |
module or1200_iwb_biu();
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// THIS MODULE IS OBSOLETE !!!
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// COMPLETELY REWRITTEN or1200_wb_biu.v IS USED INSTEAD !!!
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endmodule
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