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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_iwb_biu.v] - Blame information for rev 277

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's WISHBONE BIU                                       ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://opencores.org/project,or1k                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Implements WISHBONE interface                               ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - if biu_cyc/stb are deasserted and wb_ack_i is asserted   ////
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////   and this happens even before aborted_r is asssrted,        ////
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////   wb_ack_i will be delivered even though transfer is         ////
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////   internally considered already aborted. However most        ////
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////   wb_ack_i are externally registered and delayed. Normally   ////
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////   this shouldn't cause any problems.                         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Log: or1200_iwb_biu.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// Major update: 
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// This module is obsolete.
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_iwb_biu();
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        // THIS MODULE IS OBSOLETE !!! 
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        // COMPLETELY REWRITTEN or1200_wb_biu.v IS USED INSTEAD !!!
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endmodule

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