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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_lsu.v] - Blame information for rev 156

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Load/Store unit                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Interface between CPU and DC.                               ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_lsu.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Structure reordered and bugs fixed. 
//
// Revision 1.5  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.4  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/11/30 18:59:47  simons
// *** empty log message ***
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_lsu(
        // Clock and Reset
        clk, rst,
 
        // Internal i/f
        id_addrbase, ex_addrbase, id_addrofs, ex_addrofs, id_lsu_op,
        lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
        du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
        id_freeze, ex_freeze, flushpipe,
 
        // External i/f to DC
        dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
        dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Internal i/f
//
input   [31:0]                   id_addrbase;
input   [31:0]                   ex_addrbase;
input   [31:0]                   id_addrofs;
input   [31:0]                   ex_addrofs;
input   [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
input   [dw-1:0]         lsu_datain;
output  [dw-1:0]         lsu_dataout;
output                          lsu_stall;
output                          lsu_unstall;
input                           du_stall;
output                          except_align;
output                          except_dtlbmiss;
output                          except_dmmufault;
output                          except_dbuserr;
input                           id_freeze;
input                           ex_freeze;
input                           flushpipe;
 
//
// External i/f to DC
//
output  [31:0]                   dcpu_adr_o;
output                          dcpu_cycstb_o;
output                          dcpu_we_o;
output  [3:0]                    dcpu_sel_o;
output  [3:0]                    dcpu_tag_o;
output  [31:0]                   dcpu_dat_o;
input   [31:0]                   dcpu_dat_i;
input                           dcpu_ack_i;
input                           dcpu_rty_i;
input                           dcpu_err_i;
input   [3:0]                    dcpu_tag_i;
 
//
// Internal wires/regs
//
reg     [3:0]                    dcpu_sel_o;
 
reg     [`OR1200_LSUOP_WIDTH-1:0] ex_lsu_op;
wire    [`OR1200_LSUEA_PRECALC:0] id_precalc_sum;
reg     [`OR1200_LSUEA_PRECALC:0] dcpu_adr_r;
reg                             except_align;
 
//
// ex_lsu_op
//
always @(posedge clk or posedge rst) begin
    if (rst)
        ex_lsu_op <= #1 `OR1200_LSUOP_NOP;
    else if (!ex_freeze & id_freeze | flushpipe)
        ex_lsu_op <= #1 `OR1200_LSUOP_NOP;
    else if (!ex_freeze)
        ex_lsu_op <= #1 id_lsu_op;
end
 
//
// Precalculate part of load/store EA in ID stage
//
assign id_precalc_sum = id_addrbase[`OR1200_LSUEA_PRECALC-1:0] +
                        id_addrofs[`OR1200_LSUEA_PRECALC-1:0];
 
always @(posedge clk or posedge rst) begin
    if (rst)
        dcpu_adr_r <= #1 {`OR1200_LSUEA_PRECALC{1'b0}};
    else if (!ex_freeze)
        dcpu_adr_r <= #1 id_precalc_sum;
end
 
//
// Generate except_align in ID stage
//
always @(posedge clk or posedge rst) begin
    if (rst)
        except_align <= #1 1'b0;
    else if (!ex_freeze & id_freeze | flushpipe)
        except_align <= #1 1'b0;
    else if (!ex_freeze)
        except_align <= #1 ((id_lsu_op == `OR1200_LSUOP_SH) |
                            (id_lsu_op == `OR1200_LSUOP_LHZ) |
                            (id_lsu_op == `OR1200_LSUOP_LHS)) & id_precalc_sum[0]
                        |  ((id_lsu_op == `OR1200_LSUOP_SW) |
                            (id_lsu_op == `OR1200_LSUOP_LWZ) |
                            (id_lsu_op == `OR1200_LSUOP_LWS)) & |id_precalc_sum[1:0];
end
 
//
// Internal I/F assignments
//
assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;
assign lsu_unstall = dcpu_ack_i;
assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
 
//
// External I/F assignments
//
assign dcpu_adr_o[31:`OR1200_LSUEA_PRECALC] = ex_addrbase[31:`OR1200_LSUEA_PRECALC] +
                                              ex_addrofs[31:`OR1200_LSUEA_PRECALC] +
                                              dcpu_adr_r[`OR1200_LSUEA_PRECALC]; // carry
assign dcpu_adr_o[`OR1200_LSUEA_PRECALC-1:0] = dcpu_adr_r[`OR1200_LSUEA_PRECALC-1:0];
assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ? 1'b0 : |ex_lsu_op;
assign dcpu_we_o = ex_lsu_op[3];
assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
always @(ex_lsu_op or dcpu_adr_o)
        casex({ex_lsu_op, dcpu_adr_o[1:0]})
                {`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
                {`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
                {`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
                {`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001;
                {`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100;
                {`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011;
                {`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111;
                {`OR1200_LSUOP_LBZ, 2'b00}, {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000;
                {`OR1200_LSUOP_LBZ, 2'b01}, {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100;
                {`OR1200_LSUOP_LBZ, 2'b10}, {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010;
                {`OR1200_LSUOP_LBZ, 2'b11}, {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001;
                {`OR1200_LSUOP_LHZ, 2'b00}, {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100;
                {`OR1200_LSUOP_LHZ, 2'b10}, {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011;
                {`OR1200_LSUOP_LWZ, 2'b00}, {`OR1200_LSUOP_LWS, 2'b00} : dcpu_sel_o = 4'b1111;
                default : dcpu_sel_o = 4'b0000;
        endcase
 
//
// Instantiation of Memory-to-regfile aligner
//
or1200_mem2reg or1200_mem2reg(
        .addr(dcpu_adr_o[1:0]),
        .lsu_op(ex_lsu_op),
        .memdata(dcpu_dat_i),
        .regdata(lsu_dataout)
);
 
//
// Instantiation of Regfile-to-memory aligner
//
or1200_reg2mem or1200_reg2mem(
        .addr(dcpu_adr_o[1:0]),
        .lsu_op(ex_lsu_op),
        .regdata(lsu_datain),
        .memdata(dcpu_dat_o)
);
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Load/Store unit ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Interface between CPU and DC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	141	marcus.erl	`// $Log: or1200_lsu.v,v $`
47			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
48			`// Major update:`
49			`// Structure reordered and bugs fixed.`
50			`//`
51			`// Revision 1.5 2004/04/05 08:29:57 lampret`
52			`// Merged branch_qmem into main tree.`
53			`//`
54	10	unneback	`// Revision 1.4 2002/03/29 15:16:56 lampret`
55			`// Some of the warnings fixed.`
56			`//`
57			`// Revision 1.3 2002/02/11 04:33:17 lampret`
58			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
59			`//`
60			`// Revision 1.2 2002/01/18 07:56:00 lampret`
61			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
62			`//`
63			`// Revision 1.1 2002/01/03 08:16:15 lampret`
64			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
65			`//`
66			`// Revision 1.9 2001/11/30 18:59:47 simons`
67			`// * empty log message *`
68			`//`
69			`// Revision 1.8 2001/10/21 17:57:16 lampret`
70			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
71			`//`
72			`// Revision 1.7 2001/10/14 13:12:09 lampret`
73			`// MP3 version.`
74			`//`
75			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
76			`// no message`
77			`//`
78			`// Revision 1.2 2001/08/09 13:39:33 lampret`
79			`// Major clean-up.`
80			`//`
81			`// Revision 1.1 2001/07/20 00:46:03 lampret`
82			`// Development version of RTL. Libraries are missing.`
83			`//`
84			`//`
85
86			`// synopsys translate_off`
87			`include "timescale.v"
88			`// synopsys translate_on`
89			`include "or1200_defines.v"
90
91			`module or1200_lsu(`
92	141	marcus.erl	`// Clock and Reset`
93			`clk, rst,`
94	10	unneback
95			`// Internal i/f`
96	141	marcus.erl	`id_addrbase, ex_addrbase, id_addrofs, ex_addrofs, id_lsu_op,`
97			`lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,`
98			`du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,`
99			`id_freeze, ex_freeze, flushpipe,`
100	10	unneback
101			`// External i/f to DC`
102			`dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,`
103			`dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i`
104			`);`
105
106			parameter dw = `OR1200_OPERAND_WIDTH;
107			parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
108
109			`//`
110			`// I/O`
111			`//`
112
113			`//`
114	141	marcus.erl	`// Clock and reset`
115			`//`
116			`input clk;`
117			`input rst;`
118
119			`//`
120	10	unneback	`// Internal i/f`
121			`//`
122	141	marcus.erl	`input [31:0] id_addrbase;`
123			`input [31:0] ex_addrbase;`
124			`input [31:0] id_addrofs;`
125			`input [31:0] ex_addrofs;`
126			input [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
127	10	unneback	`input [dw-1:0] lsu_datain;`
128			`output [dw-1:0] lsu_dataout;`
129			`output lsu_stall;`
130			`output lsu_unstall;`
131			`input du_stall;`
132			`output except_align;`
133			`output except_dtlbmiss;`
134			`output except_dmmufault;`
135			`output except_dbuserr;`
136	141	marcus.erl	`input id_freeze;`
137			`input ex_freeze;`
138			`input flushpipe;`
139	10	unneback
140			`//`
141			`// External i/f to DC`
142			`//`
143			`output [31:0] dcpu_adr_o;`
144			`output dcpu_cycstb_o;`
145			`output dcpu_we_o;`
146			`output [3:0] dcpu_sel_o;`
147			`output [3:0] dcpu_tag_o;`
148			`output [31:0] dcpu_dat_o;`
149			`input [31:0] dcpu_dat_i;`
150			`input dcpu_ack_i;`
151			`input dcpu_rty_i;`
152			`input dcpu_err_i;`
153			`input [3:0] dcpu_tag_i;`
154
155			`//`
156			`// Internal wires/regs`
157			`//`
158			`reg [3:0] dcpu_sel_o;`
159
160	141	marcus.erl	reg [`OR1200_LSUOP_WIDTH-1:0] ex_lsu_op;
161			wire [`OR1200_LSUEA_PRECALC:0] id_precalc_sum;
162			reg [`OR1200_LSUEA_PRECALC:0] dcpu_adr_r;
163			`reg except_align;`
164
165	10	unneback	`//`
166	141	marcus.erl	`// ex_lsu_op`
167			`//`
168			`always @(posedge clk or posedge rst) begin`
169			`if (rst)`
170			ex_lsu_op <= #1 `OR1200_LSUOP_NOP;
171			`else if (!ex_freeze & id_freeze \| flushpipe)`
172			ex_lsu_op <= #1 `OR1200_LSUOP_NOP;
173			`else if (!ex_freeze)`
174			`ex_lsu_op <= #1 id_lsu_op;`
175			`end`
176
177			`//`
178			`// Precalculate part of load/store EA in ID stage`
179			`//`
180			assign id_precalc_sum = id_addrbase[`OR1200_LSUEA_PRECALC-1:0] +
181			id_addrofs[`OR1200_LSUEA_PRECALC-1:0];
182
183			`always @(posedge clk or posedge rst) begin`
184			`if (rst)`
185			dcpu_adr_r <= #1 {`OR1200_LSUEA_PRECALC{1'b0}};
186			`else if (!ex_freeze)`
187			`dcpu_adr_r <= #1 id_precalc_sum;`
188			`end`
189
190			`//`
191			`// Generate except_align in ID stage`
192			`//`
193			`always @(posedge clk or posedge rst) begin`
194			`if (rst)`
195			`except_align <= #1 1'b0;`
196			`else if (!ex_freeze & id_freeze \| flushpipe)`
197			`except_align <= #1 1'b0;`
198			`else if (!ex_freeze)`
199			except_align <= #1 ((id_lsu_op == `OR1200_LSUOP_SH) \|
200			(id_lsu_op == `OR1200_LSUOP_LHZ) \|
201			(id_lsu_op == `OR1200_LSUOP_LHS)) & id_precalc_sum[0]
202			\| ((id_lsu_op == `OR1200_LSUOP_SW) \|
203			(id_lsu_op == `OR1200_LSUOP_LWZ) \|
204			(id_lsu_op == `OR1200_LSUOP_LWS)) & \|id_precalc_sum[1:0];
205			`end`
206
207			`//`
208	10	unneback	`// Internal I/F assignments`
209			`//`
210			`assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;`
211			`assign lsu_unstall = dcpu_ack_i;`
212			assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
213			assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
214			assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
215
216			`//`
217			`// External I/F assignments`
218			`//`
219	141	marcus.erl	assign dcpu_adr_o[31:`OR1200_LSUEA_PRECALC] = ex_addrbase[31:`OR1200_LSUEA_PRECALC] +
220			ex_addrofs[31:`OR1200_LSUEA_PRECALC] +
221			dcpu_adr_r[`OR1200_LSUEA_PRECALC]; // carry
222			assign dcpu_adr_o[`OR1200_LSUEA_PRECALC-1:0] = dcpu_adr_r[`OR1200_LSUEA_PRECALC-1:0];
223			`assign dcpu_cycstb_o = du_stall \| lsu_unstall \| except_align ? 1'b0 : \|ex_lsu_op;`
224			`assign dcpu_we_o = ex_lsu_op[3];`
225	10	unneback	assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
226	141	marcus.erl	`always @(ex_lsu_op or dcpu_adr_o)`
227			`casex({ex_lsu_op, dcpu_adr_o[1:0]})`
228	10	unneback	{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
229			{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
230			{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
231			{`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001;
232			{`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100;
233			{`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011;
234			{`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111;
235			{`OR1200_LSUOP_LBZ, 2'b00}, {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000;
236			{`OR1200_LSUOP_LBZ, 2'b01}, {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100;
237			{`OR1200_LSUOP_LBZ, 2'b10}, {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010;
238			{`OR1200_LSUOP_LBZ, 2'b11}, {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001;
239			{`OR1200_LSUOP_LHZ, 2'b00}, {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100;
240			{`OR1200_LSUOP_LHZ, 2'b10}, {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011;
241			{`OR1200_LSUOP_LWZ, 2'b00}, {`OR1200_LSUOP_LWS, 2'b00} : dcpu_sel_o = 4'b1111;
242			`default : dcpu_sel_o = 4'b0000;`
243			`endcase`
244
245			`//`
246			`// Instantiation of Memory-to-regfile aligner`
247			`//`
248			`or1200_mem2reg or1200_mem2reg(`
249			`.addr(dcpu_adr_o[1:0]),`
250	141	marcus.erl	`.lsu_op(ex_lsu_op),`
251	10	unneback	`.memdata(dcpu_dat_i),`
252			`.regdata(lsu_dataout)`
253			`);`
254
255			`//`
256			`// Instantiation of Regfile-to-memory aligner`
257			`//`
258			`or1200_reg2mem or1200_reg2mem(`
259			`.addr(dcpu_adr_o[1:0]),`
260	141	marcus.erl	`.lsu_op(ex_lsu_op),`
261	10	unneback	`.regdata(lsu_datain),`
262			`.memdata(dcpu_dat_o)`
263			`);`
264
265			`endmodule`

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