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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mem2reg.v] - Blame information for rev 364

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1 10 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's mem2reg alignment                                  ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Two versions of Memory to register data alignment.          ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
45
//
46 141 marcus.erl
// $Log: or1200_mem2reg.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// No update 
49
//
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// Revision 1.5  2002/09/03 22:28:21  lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
52
//
53 10 unneback
// Revision 1.4  2002/03/29 15:16:56  lampret
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// Some of the warnings fixed.
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//
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// Revision 1.3  2002/03/28 19:14:10  lampret
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// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
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//
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// Revision 1.2  2002/01/14 06:18:22  lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
61
//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.9  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.8  2001/10/19 23:28:46  lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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//
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// Revision 1.7  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.2  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
84
 
85
// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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90
module or1200_mem2reg(addr, lsu_op, memdata, regdata);
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92
parameter width = `OR1200_OPERAND_WIDTH;
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94
//
95
// I/O
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//
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input   [1:0]                    addr;
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input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
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input   [width-1:0]              memdata;
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output  [width-1:0]              regdata;
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102
 
103
//
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// In the past faster implementation of mem2reg (today probably slower)
105
//
106
`ifdef OR1200_IMPL_MEM2REG2
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108
`define OR1200_M2R_BYTE0 4'b0000
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`define OR1200_M2R_BYTE1 4'b0001
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`define OR1200_M2R_BYTE2 4'b0010
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`define OR1200_M2R_BYTE3 4'b0011
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`define OR1200_M2R_EXTB0 4'b0100
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`define OR1200_M2R_EXTB1 4'b0101
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`define OR1200_M2R_EXTB2 4'b0110
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`define OR1200_M2R_EXTB3 4'b0111
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`define OR1200_M2R_ZERO  4'b0000
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118
reg     [7:0]                    regdata_hh;
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reg     [7:0]                    regdata_hl;
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reg     [7:0]                    regdata_lh;
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reg     [7:0]                    regdata_ll;
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reg     [width-1:0]              aligned;
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reg     [3:0]                    sel_byte0, sel_byte1,
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                                sel_byte2, sel_byte3;
125
 
126
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
127
 
128
//
129
// Byte select 0
130
//
131
always @(addr or lsu_op) begin
132
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
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                {3'b01x, 2'b00}:                        // lbz/lbs 0
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                        sel_byte0 = `OR1200_M2R_BYTE3;  // take byte 3
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                {3'b01x, 2'b01},                        // lbz/lbs 1
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                {3'b10x, 2'b00}:                        // lhz/lhs 0
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                        sel_byte0 = `OR1200_M2R_BYTE2;  // take byte 2
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                {3'b01x, 2'b10}:                        // lbz/lbs 2
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                        sel_byte0 = `OR1200_M2R_BYTE1;  // take byte 1
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                default:                                // all other cases
141
                        sel_byte0 = `OR1200_M2R_BYTE0;  // take byte 0
142
        endcase
143
end
144
 
145
//
146
// Byte select 1
147
//
148
always @(addr or lsu_op) begin
149
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
150
                {3'b010, 2'bxx}:                        // lbz
151
                        sel_byte1 = `OR1200_M2R_ZERO;   // zero extend
152
                {3'b011, 2'b00}:                        // lbs 0
153
                        sel_byte1 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
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                {3'b011, 2'b01}:                        // lbs 1
155
                        sel_byte1 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
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                {3'b011, 2'b10}:                        // lbs 2
157
                        sel_byte1 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
158
                {3'b011, 2'b11}:                        // lbs 3
159
                        sel_byte1 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
160
                {3'b10x, 2'b00}:                        // lhz/lhs 0
161
                        sel_byte1 = `OR1200_M2R_BYTE3;  // take byte 3
162
                default:                                // all other cases
163
                        sel_byte1 = `OR1200_M2R_BYTE1;  // take byte 1
164
        endcase
165
end
166
 
167
//
168
// Byte select 2
169
//
170
always @(addr or lsu_op) begin
171
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
172
                {3'b010, 2'bxx},                        // lbz
173
                {3'b100, 2'bxx}:                        // lhz
174
                        sel_byte2 = `OR1200_M2R_ZERO;   // zero extend
175
                {3'b011, 2'b00},                        // lbs 0
176
                {3'b101, 2'b00}:                        // lhs 0
177
                        sel_byte2 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
178
                {3'b011, 2'b01}:                        // lbs 1
179
                        sel_byte2 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
180
                {3'b011, 2'b10},                        // lbs 2
181
                {3'b101, 2'b10}:                        // lhs 0
182
                        sel_byte2 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
183
                {3'b011, 2'b11}:                        // lbs 3
184
                        sel_byte2 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
185
                default:                                // all other cases
186
                        sel_byte2 = `OR1200_M2R_BYTE2;  // take byte 2
187
        endcase
188
end
189
 
190
//
191
// Byte select 3
192
//
193
always @(addr or lsu_op) begin
194
        casex({lsu_op[2:0], addr}) // synopsys parallel_case
195
                {3'b010, 2'bxx},                        // lbz
196
                {3'b100, 2'bxx}:                        // lhz
197
                        sel_byte3 = `OR1200_M2R_ZERO;   // zero extend
198
                {3'b011, 2'b00},                        // lbs 0
199
                {3'b101, 2'b00}:                        // lhs 0
200
                        sel_byte3 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
201
                {3'b011, 2'b01}:                        // lbs 1
202
                        sel_byte3 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
203
                {3'b011, 2'b10},                        // lbs 2
204
                {3'b101, 2'b10}:                        // lhs 0
205
                        sel_byte3 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
206
                {3'b011, 2'b11}:                        // lbs 3
207
                        sel_byte3 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
208
                default:                                // all other cases
209
                        sel_byte3 = `OR1200_M2R_BYTE3;  // take byte 3
210
        endcase
211
end
212
 
213
//
214
// Byte 0
215
//
216
always @(sel_byte0 or memdata) begin
217
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
218
`ifdef OR1200_CASE_DEFAULT
219
        case(sel_byte0) // synopsys parallel_case infer_mux
220
`else
221
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
222
`endif
223
`else
224
`ifdef OR1200_CASE_DEFAULT
225
        case(sel_byte0) // synopsys parallel_case
226
`else
227
        case(sel_byte0) // synopsys full_case parallel_case
228
`endif
229
`endif
230
                `OR1200_M2R_BYTE0: begin
231
                                regdata_ll = memdata[7:0];
232
                        end
233
                `OR1200_M2R_BYTE1: begin
234
                                regdata_ll = memdata[15:8];
235
                        end
236
                `OR1200_M2R_BYTE2: begin
237
                                regdata_ll = memdata[23:16];
238
                        end
239
`ifdef OR1200_CASE_DEFAULT
240
                default: begin
241
`else
242
                `OR1200_M2R_BYTE3: begin
243
`endif
244
                                regdata_ll = memdata[31:24];
245
                        end
246
        endcase
247
end
248
 
249
//
250
// Byte 1
251
//
252
always @(sel_byte1 or memdata) begin
253
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
254
`ifdef OR1200_CASE_DEFAULT
255
        case(sel_byte1) // synopsys parallel_case infer_mux
256
`else
257
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
258
`endif
259
`else
260
`ifdef OR1200_CASE_DEFAULT
261
        case(sel_byte1) // synopsys parallel_case
262
`else
263
        case(sel_byte1) // synopsys full_case parallel_case
264
`endif
265
`endif
266
                `OR1200_M2R_ZERO: begin
267
                                regdata_lh = 8'h00;
268
                        end
269
                `OR1200_M2R_BYTE1: begin
270
                                regdata_lh = memdata[15:8];
271
                        end
272
                `OR1200_M2R_BYTE3: begin
273
                                regdata_lh = memdata[31:24];
274
                        end
275
                `OR1200_M2R_EXTB0: begin
276
                                regdata_lh = {8{memdata[7]}};
277
                        end
278
                `OR1200_M2R_EXTB1: begin
279
                                regdata_lh = {8{memdata[15]}};
280
                        end
281
                `OR1200_M2R_EXTB2: begin
282
                                regdata_lh = {8{memdata[23]}};
283
                        end
284
`ifdef OR1200_CASE_DEFAULT
285
                default: begin
286
`else
287
                `OR1200_M2R_EXTB3: begin
288
`endif
289
                                regdata_lh = {8{memdata[31]}};
290
                        end
291
        endcase
292
end
293
 
294
//
295
// Byte 2
296
//
297
always @(sel_byte2 or memdata) begin
298
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
299
`ifdef OR1200_CASE_DEFAULT
300
        case(sel_byte2) // synopsys parallel_case infer_mux
301
`else
302
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
303
`endif
304
`else
305
`ifdef OR1200_CASE_DEFAULT
306
        case(sel_byte2) // synopsys parallel_case
307
`else
308
        case(sel_byte2) // synopsys full_case parallel_case
309
`endif
310
`endif
311
                `OR1200_M2R_ZERO: begin
312
                                regdata_hl = 8'h00;
313
                        end
314
                `OR1200_M2R_BYTE2: begin
315
                                regdata_hl = memdata[23:16];
316
                        end
317
                `OR1200_M2R_EXTB0: begin
318
                                regdata_hl = {8{memdata[7]}};
319
                        end
320
                `OR1200_M2R_EXTB1: begin
321
                                regdata_hl = {8{memdata[15]}};
322
                        end
323
                `OR1200_M2R_EXTB2: begin
324
                                regdata_hl = {8{memdata[23]}};
325
                        end
326
`ifdef OR1200_CASE_DEFAULT
327
                default: begin
328
`else
329
                `OR1200_M2R_EXTB3: begin
330
`endif
331
                                regdata_hl = {8{memdata[31]}};
332
                        end
333
        endcase
334
end
335
 
336
//
337
// Byte 3
338
//
339
always @(sel_byte3 or memdata) begin
340
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
341
`ifdef OR1200_CASE_DEFAULT
342
        case(sel_byte3) // synopsys parallel_case infer_mux
343
`else
344
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
345
`endif
346
`else
347
`ifdef OR1200_CASE_DEFAULT
348
        case(sel_byte3) // synopsys parallel_case
349
`else
350
        case(sel_byte3) // synopsys full_case parallel_case
351
`endif
352
`endif
353
                `OR1200_M2R_ZERO: begin
354
                                regdata_hh = 8'h00;
355
                        end
356
                `OR1200_M2R_BYTE3: begin
357
                                regdata_hh = memdata[31:24];
358
                        end
359
                `OR1200_M2R_EXTB0: begin
360
                                regdata_hh = {8{memdata[7]}};
361
                        end
362
                `OR1200_M2R_EXTB1: begin
363
                                regdata_hh = {8{memdata[15]}};
364
                        end
365
                `OR1200_M2R_EXTB2: begin
366
                                regdata_hh = {8{memdata[23]}};
367
                        end
368
`ifdef OR1200_CASE_DEFAULT
369
                `OR1200_M2R_EXTB3: begin
370
`else
371
                `OR1200_M2R_EXTB3: begin
372
`endif
373
                                regdata_hh = {8{memdata[31]}};
374
                        end
375
        endcase
376
end
377
 
378
`else
379
 
380
//
381
// Straightforward implementation of mem2reg
382
//
383
 
384
reg     [width-1:0]              regdata;
385
reg     [width-1:0]              aligned;
386
 
387
//
388
// Alignment
389
//
390
always @(addr or memdata) begin
391
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
392
        case(addr) // synopsys parallel_case infer_mux
393
`else
394
        case(addr) // synopsys parallel_case
395
`endif
396
                2'b00:
397
                        aligned = memdata;
398
                2'b01:
399
                        aligned = {memdata[23:0], 8'b0};
400
                2'b10:
401
                        aligned = {memdata[15:0], 16'b0};
402
                2'b11:
403
                        aligned = {memdata[7:0], 24'b0};
404
        endcase
405
end
406
 
407
//
408
// Bytes
409
//
410
always @(lsu_op or aligned) begin
411
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
412
        case(lsu_op) // synopsys parallel_case infer_mux
413
`else
414
        case(lsu_op) // synopsys parallel_case
415
`endif
416
                `OR1200_LSUOP_LBZ: begin
417
                                regdata[7:0] = aligned[31:24];
418
                                regdata[31:8] = 24'b0;
419
                        end
420
                `OR1200_LSUOP_LBS: begin
421
                                regdata[7:0] = aligned[31:24];
422
                                regdata[31:8] = {24{aligned[31]}};
423
                        end
424
                `OR1200_LSUOP_LHZ: begin
425
                                regdata[15:0] = aligned[31:16];
426
                                regdata[31:16] = 16'b0;
427
                        end
428
                `OR1200_LSUOP_LHS: begin
429
                                regdata[15:0] = aligned[31:16];
430
                                regdata[31:16] = {16{aligned[31]}};
431
                        end
432
                default:
433
                                regdata = aligned;
434
        endcase
435
end
436
 
437
`endif
438
 
439
endmodule

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