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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mem2reg.v] - Blame information for rev 169

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's mem2reg alignment                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Two versions of Memory to register data alignment.          ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_mem2reg.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// No update 
//
// Revision 1.5  2002/09/03 22:28:21  lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.4  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/03/28 19:14:10  lampret
// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_mem2reg(addr, lsu_op, memdata, regdata);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
input   [width-1:0]              memdata;
output  [width-1:0]              regdata;
 
 
//
// In the past faster implementation of mem2reg (today probably slower)
//
`ifdef OR1200_IMPL_MEM2REG2
 
`define OR1200_M2R_BYTE0 4'b0000
`define OR1200_M2R_BYTE1 4'b0001
`define OR1200_M2R_BYTE2 4'b0010
`define OR1200_M2R_BYTE3 4'b0011
`define OR1200_M2R_EXTB0 4'b0100
`define OR1200_M2R_EXTB1 4'b0101
`define OR1200_M2R_EXTB2 4'b0110
`define OR1200_M2R_EXTB3 4'b0111
`define OR1200_M2R_ZERO  4'b0000
 
reg     [7:0]                    regdata_hh;
reg     [7:0]                    regdata_hl;
reg     [7:0]                    regdata_lh;
reg     [7:0]                    regdata_ll;
reg     [width-1:0]              aligned;
reg     [3:0]                    sel_byte0, sel_byte1,
                                sel_byte2, sel_byte3;
 
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
 
//
// Byte select 0
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b01x, 2'b00}:                        // lbz/lbs 0
                        sel_byte0 = `OR1200_M2R_BYTE3;  // take byte 3
                {3'b01x, 2'b01},                        // lbz/lbs 1
                {3'b10x, 2'b00}:                        // lhz/lhs 0
                        sel_byte0 = `OR1200_M2R_BYTE2;  // take byte 2
                {3'b01x, 2'b10}:                        // lbz/lbs 2
                        sel_byte0 = `OR1200_M2R_BYTE1;  // take byte 1
                default:                                // all other cases
                        sel_byte0 = `OR1200_M2R_BYTE0;  // take byte 0
        endcase
end
 
//
// Byte select 1
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx}:                        // lbz
                        sel_byte1 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00}:                        // lbs 0
                        sel_byte1 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte1 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10}:                        // lbs 2
                        sel_byte1 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte1 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                {3'b10x, 2'b00}:                        // lhz/lhs 0
                        sel_byte1 = `OR1200_M2R_BYTE3;  // take byte 3
                default:                                // all other cases
                        sel_byte1 = `OR1200_M2R_BYTE1;  // take byte 1
        endcase
end
 
//
// Byte select 2
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr})       // synopsys parallel_case
                {3'b010, 2'bxx},                        // lbz
                {3'b100, 2'bxx}:                        // lhz
                        sel_byte2 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00},                        // lbs 0
                {3'b101, 2'b00}:                        // lhs 0
                        sel_byte2 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte2 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10},                        // lbs 2
                {3'b101, 2'b10}:                        // lhs 0
                        sel_byte2 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte2 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                default:                                // all other cases
                        sel_byte2 = `OR1200_M2R_BYTE2;  // take byte 2
        endcase
end
 
//
// Byte select 3
//
always @(addr or lsu_op) begin
        casex({lsu_op[2:0], addr}) // synopsys parallel_case
                {3'b010, 2'bxx},                        // lbz
                {3'b100, 2'bxx}:                        // lhz
                        sel_byte3 = `OR1200_M2R_ZERO;   // zero extend
                {3'b011, 2'b00},                        // lbs 0
                {3'b101, 2'b00}:                        // lhs 0
                        sel_byte3 = `OR1200_M2R_EXTB3;  // sign extend from byte 3
                {3'b011, 2'b01}:                        // lbs 1
                        sel_byte3 = `OR1200_M2R_EXTB2;  // sign extend from byte 2
                {3'b011, 2'b10},                        // lbs 2
                {3'b101, 2'b10}:                        // lhs 0
                        sel_byte3 = `OR1200_M2R_EXTB1;  // sign extend from byte 1
                {3'b011, 2'b11}:                        // lbs 3
                        sel_byte3 = `OR1200_M2R_EXTB0;  // sign extend from byte 0
                default:                                // all other cases
                        sel_byte3 = `OR1200_M2R_BYTE3;  // take byte 3
        endcase
end
 
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte0) // synopsys parallel_case infer_mux
`else
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte0) // synopsys parallel_case
`else
        case(sel_byte0) // synopsys full_case parallel_case
`endif
`endif
                `OR1200_M2R_BYTE0: begin
                                regdata_ll = memdata[7:0];
                        end
                `OR1200_M2R_BYTE1: begin
                                regdata_ll = memdata[15:8];
                        end
                `OR1200_M2R_BYTE2: begin
                                regdata_ll = memdata[23:16];
                        end
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_M2R_BYTE3: begin
`endif
                                regdata_ll = memdata[31:24];
                        end
        endcase
end
 
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte1) // synopsys parallel_case infer_mux
`else
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte1) // synopsys parallel_case
`else
        case(sel_byte1) // synopsys full_case parallel_case
`endif
`endif
                `OR1200_M2R_ZERO: begin
                                regdata_lh = 8'h00;
                        end
                `OR1200_M2R_BYTE1: begin
                                regdata_lh = memdata[15:8];
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_lh = memdata[31:24];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_lh = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_lh = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_lh = {8{memdata[23]}};
                        end
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_M2R_EXTB3: begin
`endif
                                regdata_lh = {8{memdata[31]}};
                        end
        endcase
end
 
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte2) // synopsys parallel_case infer_mux
`else
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte2) // synopsys parallel_case
`else
        case(sel_byte2) // synopsys full_case parallel_case
`endif
`endif
                `OR1200_M2R_ZERO: begin
                                regdata_hl = 8'h00;
                        end
                `OR1200_M2R_BYTE2: begin
                                regdata_hl = memdata[23:16];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_hl = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_hl = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_hl = {8{memdata[23]}};
                        end
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_M2R_EXTB3: begin
`endif
                                regdata_hl = {8{memdata[31]}};
                        end
        endcase
end
 
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte3) // synopsys parallel_case infer_mux
`else
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
        case(sel_byte3) // synopsys parallel_case
`else
        case(sel_byte3) // synopsys full_case parallel_case
`endif
`endif
                `OR1200_M2R_ZERO: begin
                                regdata_hh = 8'h00;
                        end
                `OR1200_M2R_BYTE3: begin
                                regdata_hh = memdata[31:24];
                        end
                `OR1200_M2R_EXTB0: begin
                                regdata_hh = {8{memdata[7]}};
                        end
                `OR1200_M2R_EXTB1: begin
                                regdata_hh = {8{memdata[15]}};
                        end
                `OR1200_M2R_EXTB2: begin
                                regdata_hh = {8{memdata[23]}};
                        end
`ifdef OR1200_CASE_DEFAULT
                `OR1200_M2R_EXTB3: begin
`else
                `OR1200_M2R_EXTB3: begin
`endif
                                regdata_hh = {8{memdata[31]}};
                        end
        endcase
end
 
`else
 
//
// Straightforward implementation of mem2reg
//
 
reg     [width-1:0]              regdata;
reg     [width-1:0]              aligned;
 
//
// Alignment
//
always @(addr or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(addr) // synopsys parallel_case infer_mux
`else
        case(addr) // synopsys parallel_case
`endif
                2'b00:
                        aligned = memdata;
                2'b01:
                        aligned = {memdata[23:0], 8'b0};
                2'b10:
                        aligned = {memdata[15:0], 16'b0};
                2'b11:
                        aligned = {memdata[7:0], 24'b0};
        endcase
end
 
//
// Bytes
//
always @(lsu_op or aligned) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        case(lsu_op) // synopsys parallel_case infer_mux
`else
        case(lsu_op) // synopsys parallel_case
`endif
                `OR1200_LSUOP_LBZ: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = 24'b0;
                        end
                `OR1200_LSUOP_LBS: begin
                                regdata[7:0] = aligned[31:24];
                                regdata[31:8] = {24{aligned[31]}};
                        end
                `OR1200_LSUOP_LHZ: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = 16'b0;
                        end
                `OR1200_LSUOP_LHS: begin
                                regdata[15:0] = aligned[31:16];
                                regdata[31:16] = {16{aligned[31]}};
                        end
                default:
                                regdata = aligned;
        endcase
end
 
`endif
 
endmodule

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mem2reg.v] - Blame information for rev 169

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's mem2reg alignment ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Two versions of Memory to register data alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	141	marcus.erl	`// $Log: or1200_mem2reg.v,v $`
47			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
48			`// No update`
49			`//`
50			`// Revision 1.5 2002/09/03 22:28:21 lampret`
51			`// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.`
52			`//`
53	10	unneback	`// Revision 1.4 2002/03/29 15:16:56 lampret`
54			`// Some of the warnings fixed.`
55			`//`
56			`// Revision 1.3 2002/03/28 19:14:10 lampret`
57			`// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2`
58			`//`
59			`// Revision 1.2 2002/01/14 06:18:22 lampret`
60			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
61			`//`
62			`// Revision 1.1 2002/01/03 08:16:15 lampret`
63			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
64			`//`
65			`// Revision 1.9 2001/10/21 17:57:16 lampret`
66			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
67			`//`
68			`// Revision 1.8 2001/10/19 23:28:46 lampret`
69			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
70			`//`
71			`// Revision 1.7 2001/10/14 13:12:09 lampret`
72			`// MP3 version.`
73			`//`
74			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
75			`// no message`
76			`//`
77			`// Revision 1.2 2001/08/09 13:39:33 lampret`
78			`// Major clean-up.`
79			`//`
80			`// Revision 1.1 2001/07/20 00:46:03 lampret`
81			`// Development version of RTL. Libraries are missing.`
82			`//`
83			`//`
84
85			`// synopsys translate_off`
86			`include "timescale.v"
87			`// synopsys translate_on`
88			`include "or1200_defines.v"
89
90			`module or1200_mem2reg(addr, lsu_op, memdata, regdata);`
91
92			parameter width = `OR1200_OPERAND_WIDTH;
93
94			`//`
95			`// I/O`
96			`//`
97			`input [1:0] addr;`
98			input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
99			`input [width-1:0] memdata;`
100			`output [width-1:0] regdata;`
101
102
103			`//`
104			`// In the past faster implementation of mem2reg (today probably slower)`
105			`//`
106			`ifdef OR1200_IMPL_MEM2REG2
107
108			`define OR1200_M2R_BYTE0 4'b0000
109			`define OR1200_M2R_BYTE1 4'b0001
110			`define OR1200_M2R_BYTE2 4'b0010
111			`define OR1200_M2R_BYTE3 4'b0011
112			`define OR1200_M2R_EXTB0 4'b0100
113			`define OR1200_M2R_EXTB1 4'b0101
114			`define OR1200_M2R_EXTB2 4'b0110
115			`define OR1200_M2R_EXTB3 4'b0111
116			`define OR1200_M2R_ZERO 4'b0000
117
118			`reg [7:0] regdata_hh;`
119			`reg [7:0] regdata_hl;`
120			`reg [7:0] regdata_lh;`
121			`reg [7:0] regdata_ll;`
122			`reg [width-1:0] aligned;`
123			`reg [3:0] sel_byte0, sel_byte1,`
124			`sel_byte2, sel_byte3;`
125
126			`assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};`
127
128			`//`
129			`// Byte select 0`
130			`//`
131			`always @(addr or lsu_op) begin`
132			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
133			`{3'b01x, 2'b00}: // lbz/lbs 0`
134			sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3
135			`{3'b01x, 2'b01}, // lbz/lbs 1`
136			`{3'b10x, 2'b00}: // lhz/lhs 0`
137			sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2
138			`{3'b01x, 2'b10}: // lbz/lbs 2`
139			sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1
140			`default: // all other cases`
141			sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0
142			`endcase`
143			`end`
144
145			`//`
146			`// Byte select 1`
147			`//`
148			`always @(addr or lsu_op) begin`
149			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
150			`{3'b010, 2'bxx}: // lbz`
151			sel_byte1 = `OR1200_M2R_ZERO; // zero extend
152			`{3'b011, 2'b00}: // lbs 0`
153			sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3
154			`{3'b011, 2'b01}: // lbs 1`
155			sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2
156			`{3'b011, 2'b10}: // lbs 2`
157			sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1
158			`{3'b011, 2'b11}: // lbs 3`
159			sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0
160			`{3'b10x, 2'b00}: // lhz/lhs 0`
161			sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3
162			`default: // all other cases`
163			sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1
164			`endcase`
165			`end`
166
167			`//`
168			`// Byte select 2`
169			`//`
170			`always @(addr or lsu_op) begin`
171			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
172			`{3'b010, 2'bxx}, // lbz`
173			`{3'b100, 2'bxx}: // lhz`
174			sel_byte2 = `OR1200_M2R_ZERO; // zero extend
175			`{3'b011, 2'b00}, // lbs 0`
176			`{3'b101, 2'b00}: // lhs 0`
177			sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3
178			`{3'b011, 2'b01}: // lbs 1`
179			sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2
180			`{3'b011, 2'b10}, // lbs 2`
181			`{3'b101, 2'b10}: // lhs 0`
182			sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1
183			`{3'b011, 2'b11}: // lbs 3`
184			sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0
185			`default: // all other cases`
186			sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2
187			`endcase`
188			`end`
189
190			`//`
191			`// Byte select 3`
192			`//`
193			`always @(addr or lsu_op) begin`
194			`casex({lsu_op[2:0], addr}) // synopsys parallel_case`
195			`{3'b010, 2'bxx}, // lbz`
196			`{3'b100, 2'bxx}: // lhz`
197			sel_byte3 = `OR1200_M2R_ZERO; // zero extend
198			`{3'b011, 2'b00}, // lbs 0`
199			`{3'b101, 2'b00}: // lhs 0`
200			sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3
201			`{3'b011, 2'b01}: // lbs 1`
202			sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2
203			`{3'b011, 2'b10}, // lbs 2`
204			`{3'b101, 2'b10}: // lhs 0`
205			sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1
206			`{3'b011, 2'b11}: // lbs 3`
207			sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0
208			`default: // all other cases`
209			sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3
210			`endcase`
211			`end`
212
213			`//`
214			`// Byte 0`
215			`//`
216			`always @(sel_byte0 or memdata) begin`
217			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
218			`ifdef OR1200_CASE_DEFAULT
219			`case(sel_byte0) // synopsys parallel_case infer_mux`
220			`else
221			`case(sel_byte0) // synopsys full_case parallel_case infer_mux`
222			`endif
223			`else
224			`ifdef OR1200_CASE_DEFAULT
225			`case(sel_byte0) // synopsys parallel_case`
226			`else
227			`case(sel_byte0) // synopsys full_case parallel_case`
228			`endif
229			`endif
230			`OR1200_M2R_BYTE0: begin
231			`regdata_ll = memdata[7:0];`
232			`end`
233			`OR1200_M2R_BYTE1: begin
234			`regdata_ll = memdata[15:8];`
235			`end`
236			`OR1200_M2R_BYTE2: begin
237			`regdata_ll = memdata[23:16];`
238			`end`
239			`ifdef OR1200_CASE_DEFAULT
240			`default: begin`
241			`else
242			`OR1200_M2R_BYTE3: begin
243			`endif
244			`regdata_ll = memdata[31:24];`
245			`end`
246			`endcase`
247			`end`
248
249			`//`
250			`// Byte 1`
251			`//`
252			`always @(sel_byte1 or memdata) begin`
253			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
254			`ifdef OR1200_CASE_DEFAULT
255			`case(sel_byte1) // synopsys parallel_case infer_mux`
256			`else
257			`case(sel_byte1) // synopsys full_case parallel_case infer_mux`
258			`endif
259			`else
260			`ifdef OR1200_CASE_DEFAULT
261			`case(sel_byte1) // synopsys parallel_case`
262			`else
263			`case(sel_byte1) // synopsys full_case parallel_case`
264			`endif
265			`endif
266			`OR1200_M2R_ZERO: begin
267			`regdata_lh = 8'h00;`
268			`end`
269			`OR1200_M2R_BYTE1: begin
270			`regdata_lh = memdata[15:8];`
271			`end`
272			`OR1200_M2R_BYTE3: begin
273			`regdata_lh = memdata[31:24];`
274			`end`
275			`OR1200_M2R_EXTB0: begin
276			`regdata_lh = {8{memdata[7]}};`
277			`end`
278			`OR1200_M2R_EXTB1: begin
279			`regdata_lh = {8{memdata[15]}};`
280			`end`
281			`OR1200_M2R_EXTB2: begin
282			`regdata_lh = {8{memdata[23]}};`
283			`end`
284			`ifdef OR1200_CASE_DEFAULT
285			`default: begin`
286			`else
287			`OR1200_M2R_EXTB3: begin
288			`endif
289			`regdata_lh = {8{memdata[31]}};`
290			`end`
291			`endcase`
292			`end`
293
294			`//`
295			`// Byte 2`
296			`//`
297			`always @(sel_byte2 or memdata) begin`
298			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
299			`ifdef OR1200_CASE_DEFAULT
300			`case(sel_byte2) // synopsys parallel_case infer_mux`
301			`else
302			`case(sel_byte2) // synopsys full_case parallel_case infer_mux`
303			`endif
304			`else
305			`ifdef OR1200_CASE_DEFAULT
306			`case(sel_byte2) // synopsys parallel_case`
307			`else
308			`case(sel_byte2) // synopsys full_case parallel_case`
309			`endif
310			`endif
311			`OR1200_M2R_ZERO: begin
312			`regdata_hl = 8'h00;`
313			`end`
314			`OR1200_M2R_BYTE2: begin
315			`regdata_hl = memdata[23:16];`
316			`end`
317			`OR1200_M2R_EXTB0: begin
318			`regdata_hl = {8{memdata[7]}};`
319			`end`
320			`OR1200_M2R_EXTB1: begin
321			`regdata_hl = {8{memdata[15]}};`
322			`end`
323			`OR1200_M2R_EXTB2: begin
324			`regdata_hl = {8{memdata[23]}};`
325			`end`
326			`ifdef OR1200_CASE_DEFAULT
327			`default: begin`
328			`else
329			`OR1200_M2R_EXTB3: begin
330			`endif
331			`regdata_hl = {8{memdata[31]}};`
332			`end`
333			`endcase`
334			`end`
335
336			`//`
337			`// Byte 3`
338			`//`
339			`always @(sel_byte3 or memdata) begin`
340			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
341			`ifdef OR1200_CASE_DEFAULT
342			`case(sel_byte3) // synopsys parallel_case infer_mux`
343			`else
344			`case(sel_byte3) // synopsys full_case parallel_case infer_mux`
345			`endif
346			`else
347			`ifdef OR1200_CASE_DEFAULT
348			`case(sel_byte3) // synopsys parallel_case`
349			`else
350			`case(sel_byte3) // synopsys full_case parallel_case`
351			`endif
352			`endif
353			`OR1200_M2R_ZERO: begin
354			`regdata_hh = 8'h00;`
355			`end`
356			`OR1200_M2R_BYTE3: begin
357			`regdata_hh = memdata[31:24];`
358			`end`
359			`OR1200_M2R_EXTB0: begin
360			`regdata_hh = {8{memdata[7]}};`
361			`end`
362			`OR1200_M2R_EXTB1: begin
363			`regdata_hh = {8{memdata[15]}};`
364			`end`
365			`OR1200_M2R_EXTB2: begin
366			`regdata_hh = {8{memdata[23]}};`
367			`end`
368			`ifdef OR1200_CASE_DEFAULT
369			`OR1200_M2R_EXTB3: begin
370			`else
371			`OR1200_M2R_EXTB3: begin
372			`endif
373			`regdata_hh = {8{memdata[31]}};`
374			`end`
375			`endcase`
376			`end`
377
378			`else
379
380			`//`
381			`// Straightforward implementation of mem2reg`
382			`//`
383
384			`reg [width-1:0] regdata;`
385			`reg [width-1:0] aligned;`
386
387			`//`
388			`// Alignment`
389			`//`
390			`always @(addr or memdata) begin`
391			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
392			`case(addr) // synopsys parallel_case infer_mux`
393			`else
394			`case(addr) // synopsys parallel_case`
395			`endif
396			`2'b00:`
397			`aligned = memdata;`
398			`2'b01:`
399			`aligned = {memdata[23:0], 8'b0};`
400			`2'b10:`
401			`aligned = {memdata[15:0], 16'b0};`
402			`2'b11:`
403			`aligned = {memdata[7:0], 24'b0};`
404			`endcase`
405			`end`
406
407			`//`
408			`// Bytes`
409			`//`
410			`always @(lsu_op or aligned) begin`
411			`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
412			`case(lsu_op) // synopsys parallel_case infer_mux`
413			`else
414			`case(lsu_op) // synopsys parallel_case`
415			`endif
416			`OR1200_LSUOP_LBZ: begin
417			`regdata[7:0] = aligned[31:24];`
418			`regdata[31:8] = 24'b0;`
419			`end`
420			`OR1200_LSUOP_LBS: begin
421			`regdata[7:0] = aligned[31:24];`
422			`regdata[31:8] = {24{aligned[31]}};`
423			`end`
424			`OR1200_LSUOP_LHZ: begin
425			`regdata[15:0] = aligned[31:16];`
426			`regdata[31:16] = 16'b0;`
427			`end`
428			`OR1200_LSUOP_LHS: begin
429			`regdata[15:0] = aligned[31:16];`
430			`regdata[31:16] = {16{aligned[31]}};`
431			`end`
432			`default:`
433			`regdata = aligned;`
434			`endcase`
435			`end`
436
437			`endif
438
439			`endmodule`