OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_operandmuxes.v] - Blame information for rev 146

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's register file read operands mux                    ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Mux for two register file read operands.                    ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46 141 marcus.erl
// $Log: or1200_operandmuxes.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// Minor update: 
49
// Bugs fixed. 
50
//
51
// Revision 1.2  2002/03/29 15:16:56  lampret
52
// Some of the warnings fixed.
53
//
54 10 unneback
// Revision 1.1  2002/01/03 08:16:15  lampret
55
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
56
//
57
// Revision 1.9  2001/11/12 01:45:40  lampret
58
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
59
//
60
// Revision 1.8  2001/10/21 17:57:16  lampret
61
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
62
//
63
// Revision 1.7  2001/10/14 13:12:09  lampret
64
// MP3 version.
65
//
66
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
67
// no message
68
//
69
// Revision 1.2  2001/08/09 13:39:33  lampret
70
// Major clean-up.
71
//
72
// Revision 1.1  2001/07/20 00:46:05  lampret
73
// Development version of RTL. Libraries are missing.
74
//
75
//
76
 
77
// synopsys translate_off
78
`include "timescale.v"
79
// synopsys translate_on
80
`include "or1200_defines.v"
81
 
82
module or1200_operandmuxes(
83
        // Clock and reset
84
        clk, rst,
85
 
86
        // Internal i/f
87
        id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
88 141 marcus.erl
        simm, sel_a, sel_b, operand_a, operand_b, muxed_a, muxed_b
89 10 unneback
);
90
 
91
parameter width = `OR1200_OPERAND_WIDTH;
92
 
93
//
94
// I/O
95
//
96
input                           clk;
97
input                           rst;
98
input                           id_freeze;
99
input                           ex_freeze;
100
input   [width-1:0]              rf_dataa;
101
input   [width-1:0]              rf_datab;
102
input   [width-1:0]              ex_forw;
103
input   [width-1:0]              wb_forw;
104
input   [width-1:0]              simm;
105
input   [`OR1200_SEL_WIDTH-1:0]  sel_a;
106
input   [`OR1200_SEL_WIDTH-1:0]  sel_b;
107
output  [width-1:0]              operand_a;
108
output  [width-1:0]              operand_b;
109 141 marcus.erl
output  [width-1:0]              muxed_a;
110 10 unneback
output  [width-1:0]              muxed_b;
111
 
112
//
113
// Internal wires and regs
114
//
115
reg     [width-1:0]              operand_a;
116
reg     [width-1:0]              operand_b;
117
reg     [width-1:0]              muxed_a;
118
reg     [width-1:0]              muxed_b;
119
reg                             saved_a;
120
reg                             saved_b;
121
 
122
//
123
// Operand A register
124
//
125
always @(posedge clk or posedge rst) begin
126
        if (rst) begin
127
                operand_a <= #1 32'd0;
128
                saved_a <= #1 1'b0;
129
        end else if (!ex_freeze && id_freeze && !saved_a) begin
130
                operand_a <= #1 muxed_a;
131
                saved_a <= #1 1'b1;
132
        end else if (!ex_freeze && !saved_a) begin
133
                operand_a <= #1 muxed_a;
134
        end else if (!ex_freeze && !id_freeze)
135
                saved_a <= #1 1'b0;
136
end
137
 
138
//
139
// Operand B register
140
//
141
always @(posedge clk or posedge rst) begin
142
        if (rst) begin
143
                operand_b <= #1 32'd0;
144
                saved_b <= #1 1'b0;
145
        end else if (!ex_freeze && id_freeze && !saved_b) begin
146
                operand_b <= #1 muxed_b;
147
                saved_b <= #1 1'b1;
148
        end else if (!ex_freeze && !saved_b) begin
149
                operand_b <= #1 muxed_b;
150
        end else if (!ex_freeze && !id_freeze)
151
                saved_b <= #1 1'b0;
152
end
153
 
154
//
155
// Forwarding logic for operand A register
156
//
157
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
158
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
159
        casex (sel_a)   // synopsys parallel_case infer_mux
160
`else
161
        casex (sel_a)   // synopsys parallel_case
162
`endif
163
                `OR1200_SEL_EX_FORW:
164
                        muxed_a = ex_forw;
165
                `OR1200_SEL_WB_FORW:
166
                        muxed_a = wb_forw;
167
                default:
168
                        muxed_a = rf_dataa;
169
        endcase
170
end
171
 
172
//
173
// Forwarding logic for operand B register
174
//
175
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
176
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
177
        casex (sel_b)   // synopsys parallel_case infer_mux
178
`else
179
        casex (sel_b)   // synopsys parallel_case
180
`endif
181
                `OR1200_SEL_IMM:
182
                        muxed_b = simm;
183
                `OR1200_SEL_EX_FORW:
184
                        muxed_b = ex_forw;
185
                `OR1200_SEL_WB_FORW:
186
                        muxed_b = wb_forw;
187
                default:
188
                        muxed_b = rf_datab;
189
        endcase
190
end
191
 
192
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.