OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_pic.v] - Blame information for rev 151

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Programmable Interrupt Controller                  ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  PIC according to OR1K architectural specification.          ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   None                                                       ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46 141 marcus.erl
// $Log: or1200_pic.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// No update 
49
//
50
// Revision 1.4  2004/06/08 18:17:36  lampret
51
// Non-functional changes. Coding style fixes.
52
//
53 10 unneback
// Revision 1.3  2002/03/29 15:16:56  lampret
54
// Some of the warnings fixed.
55
//
56
// Revision 1.2  2002/01/18 07:56:00  lampret
57
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
58
//
59
// Revision 1.1  2002/01/03 08:16:15  lampret
60
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
61
//
62
// Revision 1.8  2001/10/21 17:57:16  lampret
63
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
64
//
65
// Revision 1.7  2001/10/14 13:12:10  lampret
66
// MP3 version.
67
//
68
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
69
// no message
70
//
71
// Revision 1.2  2001/08/09 13:39:33  lampret
72
// Major clean-up.
73
//
74
// Revision 1.1  2001/07/20 00:46:21  lampret
75
// Development version of RTL. Libraries are missing.
76
//
77
//
78
 
79
// synopsys translate_off
80
`include "timescale.v"
81
// synopsys translate_on
82
`include "or1200_defines.v"
83
 
84
module or1200_pic(
85
        // RISC Internal Interface
86
        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
87
        pic_wakeup, intr,
88
 
89
        // PIC Interface
90
        pic_int
91
);
92
 
93
//
94
// RISC Internal Interface
95
//
96
input           clk;            // Clock
97
input           rst;            // Reset
98
input           spr_cs;         // SPR CS
99
input           spr_write;      // SPR Write
100
input   [31:0]   spr_addr;       // SPR Address
101
input   [31:0]   spr_dat_i;      // SPR Write Data
102
output  [31:0]   spr_dat_o;      // SPR Read Data
103
output          pic_wakeup;     // Wakeup to the PM
104
output          intr;           // interrupt
105
                                // exception request
106
 
107
//
108
// PIC Interface
109
//
110
input   [`OR1200_PIC_INTS-1:0]   pic_int;// Interrupt inputs
111
 
112
`ifdef OR1200_PIC_IMPLEMENTED
113
 
114
//
115
// PIC Mask Register bits (or no register)
116
//
117
`ifdef OR1200_PIC_PICMR
118
reg     [`OR1200_PIC_INTS-1:2]  picmr;  // PICMR bits
119
`else
120
wire    [`OR1200_PIC_INTS-1:2]  picmr;  // No PICMR register
121
`endif
122
 
123
//
124
// PIC Status Register bits (or no register)
125
//
126
`ifdef OR1200_PIC_PICSR
127
reg     [`OR1200_PIC_INTS-1:0]   picsr;  // PICSR bits
128
`else
129
wire    [`OR1200_PIC_INTS-1:0]   picsr;  // No PICSR register
130
`endif
131
 
132
//
133
// Internal wires & regs
134
//
135
wire            picmr_sel;      // PICMR select
136
wire            picsr_sel;      // PICSR select
137
wire    [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
138
reg     [31:0]   spr_dat_o;      // SPR data out
139
 
140
//
141
// PIC registers address decoder
142
//
143
assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
144
assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
145
 
146
//
147
// Write to PICMR
148
//
149
`ifdef OR1200_PIC_PICMR
150
always @(posedge clk or posedge rst)
151
        if (rst)
152
                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
153
        else if (picmr_sel && spr_write) begin
154
                picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
155
        end
156
`else
157
assign picmr = (`OR1200_PIC_INTS)'b1;
158
`endif
159
 
160
//
161
// Write to PICSR, both CPU and external ints
162
//
163
`ifdef OR1200_PIC_PICSR
164
always @(posedge clk or posedge rst)
165
        if (rst)
166
                picsr <= {`OR1200_PIC_INTS{1'b0}};
167
        else if (picsr_sel && spr_write) begin
168
                picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
169
        end else
170
                picsr <= #1 picsr | um_ints;
171
`else
172
assign picsr = pic_int;
173
`endif
174
 
175
//
176
// Read PIC registers
177
//
178
always @(spr_addr or picmr or picsr)
179
        case (spr_addr[`OR1200_PICOFS_BITS])    // synopsys parallel_case
180
`ifdef OR1200_PIC_READREGS
181
                `OR1200_PIC_OFS_PICMR: begin
182
                                        spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
183
`ifdef OR1200_PIC_UNUSED_ZERO
184
                                        spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
185
`endif
186
                                end
187
`endif
188
                default: begin
189
                                spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
190
`ifdef OR1200_PIC_UNUSED_ZERO
191
                                spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
192
`endif
193
                        end
194
        endcase
195
 
196
//
197
// Unmasked interrupts
198
//
199
assign um_ints = pic_int & {picmr, 2'b11};
200
 
201
//
202
// Generate intr
203
//
204
assign intr = |um_ints;
205
 
206
//
207
// Assert pic_wakeup when intr is asserted
208
//
209
assign pic_wakeup = intr;
210
 
211
`else
212
 
213
//
214
// When PIC is not implemented, drive all outputs as would when PIC is disabled
215
//
216
assign intr = pic_int[1] | pic_int[0];
217
assign pic_wakeup= intr;
218
 
219
//
220
// Read PIC registers
221
//
222
`ifdef OR1200_PIC_READREGS
223
assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
224
`ifdef OR1200_PIC_UNUSED_ZERO
225
assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
226
`endif
227
`endif
228
 
229
`endif
230
 
231
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.