OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_pic.v] - Blame information for rev 588

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Programmable Interrupt Controller                  ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 258 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  PIC according to OR1K architectural specification.          ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   None                                                       ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44 141 marcus.erl
// $Log: or1200_pic.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
//
47 10 unneback
 
48
// synopsys translate_off
49
`include "timescale.v"
50
// synopsys translate_on
51
`include "or1200_defines.v"
52
 
53
module or1200_pic(
54
        // RISC Internal Interface
55
        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
56
        pic_wakeup, intr,
57
 
58
        // PIC Interface
59
        pic_int
60
);
61
 
62
//
63
// RISC Internal Interface
64
//
65
input           clk;            // Clock
66
input           rst;            // Reset
67
input           spr_cs;         // SPR CS
68
input           spr_write;      // SPR Write
69
input   [31:0]   spr_addr;       // SPR Address
70
input   [31:0]   spr_dat_i;      // SPR Write Data
71
output  [31:0]   spr_dat_o;      // SPR Read Data
72
output          pic_wakeup;     // Wakeup to the PM
73
output          intr;           // interrupt
74
                                // exception request
75
 
76
//
77
// PIC Interface
78
//
79
input   [`OR1200_PIC_INTS-1:0]   pic_int;// Interrupt inputs
80
 
81
`ifdef OR1200_PIC_IMPLEMENTED
82
 
83
//
84
// PIC Mask Register bits (or no register)
85
//
86
`ifdef OR1200_PIC_PICMR
87
reg     [`OR1200_PIC_INTS-1:2]  picmr;  // PICMR bits
88
`else
89
wire    [`OR1200_PIC_INTS-1:2]  picmr;  // No PICMR register
90
`endif
91
 
92
//
93
// PIC Status Register bits (or no register)
94
//
95
`ifdef OR1200_PIC_PICSR
96
reg     [`OR1200_PIC_INTS-1:0]   picsr;  // PICSR bits
97
`else
98
wire    [`OR1200_PIC_INTS-1:0]   picsr;  // No PICSR register
99
`endif
100
 
101
//
102
// Internal wires & regs
103
//
104
wire            picmr_sel;      // PICMR select
105
wire            picsr_sel;      // PICSR select
106
wire    [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
107
reg     [31:0]   spr_dat_o;      // SPR data out
108
 
109
//
110
// PIC registers address decoder
111
//
112
assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
113
assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
114
 
115
//
116
// Write to PICMR
117
//
118
`ifdef OR1200_PIC_PICMR
119 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
120
        if (rst == `OR1200_RST_VALUE)
121 10 unneback
                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
122
        else if (picmr_sel && spr_write) begin
123 258 julius
                picmr <=  spr_dat_i[`OR1200_PIC_INTS-1:2];
124 10 unneback
        end
125
`else
126
assign picmr = (`OR1200_PIC_INTS)'b1;
127
`endif
128
 
129
//
130
// Write to PICSR, both CPU and external ints
131
//
132
`ifdef OR1200_PIC_PICSR
133 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
134
        if (rst == `OR1200_RST_VALUE)
135 10 unneback
                picsr <= {`OR1200_PIC_INTS{1'b0}};
136
        else if (picsr_sel && spr_write) begin
137 258 julius
                picsr <=  spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
138 10 unneback
        end else
139 258 julius
                picsr <=  picsr | um_ints;
140 10 unneback
`else
141
assign picsr = pic_int;
142
`endif
143
 
144
//
145
// Read PIC registers
146
//
147
always @(spr_addr or picmr or picsr)
148
        case (spr_addr[`OR1200_PICOFS_BITS])    // synopsys parallel_case
149
`ifdef OR1200_PIC_READREGS
150
                `OR1200_PIC_OFS_PICMR: begin
151 258 julius
                   spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b11};
152
 `ifdef OR1200_PIC_UNUSED_ZERO
153
                   spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
154
 `endif
155
                end
156 10 unneback
`endif
157 258 julius
          default: begin
158
             spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
159 10 unneback
`ifdef OR1200_PIC_UNUSED_ZERO
160 258 julius
             spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
161 10 unneback
`endif
162 258 julius
          end
163 10 unneback
        endcase
164 258 julius
 
165 10 unneback
//
166
// Unmasked interrupts
167
//
168
assign um_ints = pic_int & {picmr, 2'b11};
169
 
170
//
171
// Generate intr
172
//
173
assign intr = |um_ints;
174
 
175
//
176
// Assert pic_wakeup when intr is asserted
177
//
178
assign pic_wakeup = intr;
179
 
180
`else
181
 
182
//
183
// When PIC is not implemented, drive all outputs as would when PIC is disabled
184
//
185
assign intr = pic_int[1] | pic_int[0];
186
assign pic_wakeup= intr;
187
 
188
//
189
// Read PIC registers
190
//
191
`ifdef OR1200_PIC_READREGS
192
assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
193
`ifdef OR1200_PIC_UNUSED_ZERO
194
assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
195
`endif
196
`endif
197
 
198
`endif
199
 
200
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.