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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_reg2mem.v] - Blame information for rev 36

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's reg2mem aligner                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Aligns register data to memory alignment.                   ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_reg2mem(addr, lsu_op, regdata, memdata);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
input   [width-1:0]              regdata;
output  [width-1:0]              memdata;
 
//
// Internal regs and wires
//
reg     [7:0]                    memdata_hh;
reg     [7:0]                    memdata_hl;
reg     [7:0]                    memdata_lh;
reg     [7:0]                    memdata_ll;
 
assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};
 
//
// Mux to memdata[31:24]
//
always @(lsu_op or addr or regdata) begin
        casex({lsu_op, addr[1:0]})       // synopsys parallel_case
                {`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
                {`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
                default : memdata_hh = regdata[31:24];
        endcase
end
 
//
// Mux to memdata[23:16]
//
always @(lsu_op or addr or regdata) begin
        casex({lsu_op, addr[1:0]})       // synopsys parallel_case
                {`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
                default : memdata_hl = regdata[7:0];
        endcase
end
 
//
// Mux to memdata[15:8]
//
always @(lsu_op or addr or regdata) begin
        casex({lsu_op, addr[1:0]})       // synopsys parallel_case
                {`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
                default : memdata_lh = regdata[15:8];
        endcase
end
 
//
// Mux to memdata[7:0]
//
always @(regdata)
        memdata_ll = regdata[7:0];
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's reg2mem aligner ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Aligns register data to memory alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1 2002/01/03 08:16:15 lampret`
48			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
49			`//`
50			`// Revision 1.9 2001/10/21 17:57:16 lampret`
51			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
52			`//`
53			`// Revision 1.8 2001/10/19 23:28:46 lampret`
54			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
55			`//`
56			`// Revision 1.7 2001/10/14 13:12:10 lampret`
57			`// MP3 version.`
58			`//`
59			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
60			`// no message`
61			`//`
62			`// Revision 1.2 2001/08/09 13:39:33 lampret`
63			`// Major clean-up.`
64			`//`
65			`// Revision 1.1 2001/07/20 00:46:21 lampret`
66			`// Development version of RTL. Libraries are missing.`
67			`//`
68			`//`
69
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "or1200_defines.v"
74
75			`module or1200_reg2mem(addr, lsu_op, regdata, memdata);`
76
77			parameter width = `OR1200_OPERAND_WIDTH;
78
79			`//`
80			`// I/O`
81			`//`
82			`input [1:0] addr;`
83			input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
84			`input [width-1:0] regdata;`
85			`output [width-1:0] memdata;`
86
87			`//`
88			`// Internal regs and wires`
89			`//`
90			`reg [7:0] memdata_hh;`
91			`reg [7:0] memdata_hl;`
92			`reg [7:0] memdata_lh;`
93			`reg [7:0] memdata_ll;`
94
95			`assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};`
96
97			`//`
98			`// Mux to memdata[31:24]`
99			`//`
100			`always @(lsu_op or addr or regdata) begin`
101			`casex({lsu_op, addr[1:0]}) // synopsys parallel_case`
102			{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
103			{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
104			`default : memdata_hh = regdata[31:24];`
105			`endcase`
106			`end`
107
108			`//`
109			`// Mux to memdata[23:16]`
110			`//`
111			`always @(lsu_op or addr or regdata) begin`
112			`casex({lsu_op, addr[1:0]}) // synopsys parallel_case`
113			{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
114			`default : memdata_hl = regdata[7:0];`
115			`endcase`
116			`end`
117
118			`//`
119			`// Mux to memdata[15:8]`
120			`//`
121			`always @(lsu_op or addr or regdata) begin`
122			`casex({lsu_op, addr[1:0]}) // synopsys parallel_case`
123			{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
124			`default : memdata_lh = regdata[15:8];`
125			`endcase`
126			`end`
127
128			`//`
129			`// Mux to memdata[7:0]`
130			`//`
131			`always @(regdata)`
132			`memdata_ll = regdata[7:0];`
133
134			`endmodule`

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_reg2mem.v] - Blame information for rev 36