URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rf.v] - Blame information for rev 108

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's register file inside CPU                           ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of register file memories                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/06/08 16:19:09  lampret
// Added generic flip-flop based memory macro instantiation.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.13  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.12  2001/11/13 10:02:21  lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.11  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.10  2001/11/10 03:43:57  lampret
// Fixed exceptions.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_rf(
        // Clock and reset
        clk, rst,
 
        // Write i/f
        supv, wb_freeze, addrw, dataw, we, flushpipe,
 
        // Read i/f
        id_freeze, addra, addrb, dataa, datab, rda, rdb,
 
        // Debug
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Write i/f
//
input                           supv;
input                           wb_freeze;
input   [aw-1:0]         addrw;
input   [dw-1:0]         dataw;
input                           we;
input                           flushpipe;
 
//
// Read i/f
//
input                           id_freeze;
input   [aw-1:0]         addra;
input   [aw-1:0]         addrb;
output  [dw-1:0]         dataa;
output  [dw-1:0]         datab;
input                           rda;
input                           rdb;
 
//
// SPR access for debugging purposes
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
wire    [dw-1:0]         from_rfa;
wire    [dw-1:0]         from_rfb;
reg     [dw:0]                   dataa_saved;
reg     [dw:0]                   datab_saved;
wire    [aw-1:0]         rf_addra;
wire    [aw-1:0]         rf_addrw;
wire    [dw-1:0]         rf_dataw;
wire                            rf_we;
wire                            spr_valid;
wire                            rf_ena;
wire                            rf_enb;
reg                             rf_we_allow;
 
//
// SPR access is valid when spr_cs is asserted and
// SPR address matches GPR addresses
//
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
 
//
// SPR data output is always from RF A
//
assign spr_dat_o = from_rfa;
 
//
// Operand A comes from RF or from saved A register
//
assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
 
//
// Operand B comes from RF or from saved B register
//
assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
 
//
// RF A read address is either from SPRS or normal from CPU control
//
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
 
//
// RF write address is either from SPRS or normal from CPU control
//
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
 
//
// RF write data is either from SPRS or normal from CPU datapath
//
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
 
//
// RF write enable is either from SPRS or normal from CPU control
//
always @(posedge rst or posedge clk)
        if (rst)
                rf_we_allow <= #1 1'b1;
        else if (~wb_freeze)
                rf_we_allow <= #1 ~flushpipe;
 
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
 
//
// CS RF A asserted when instruction reads operand A and ID stage
// is not stalled
//
assign rf_ena = rda & ~id_freeze | spr_valid;   // probably works with fixed binutils
// assign rf_ena = 1'b1;                        // does not work with single-stepping
//assign rf_ena = ~id_freeze | spr_valid;       // works with broken binutils 
 
//
// CS RF B asserted when instruction reads operand B and ID stage
// is not stalled
//
assign rf_enb = rdb & ~id_freeze | spr_valid;
// assign rf_enb = 1'b1;
//assign rf_enb = ~id_freeze | spr_valid;       // works with broken binutils 
 
//
// Stores operand from RF_A into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
        if (rst) begin
                dataa_saved <= #1 33'b0;
        end
        else if (id_freeze & !dataa_saved[32]) begin
                dataa_saved <= #1 {1'b1, from_rfa};
        end
        else if (!id_freeze)
                dataa_saved <= #1 33'b0;
 
//
// Stores operand from RF_B into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
        if (rst) begin
                datab_saved <= #1 33'b0;
        end
        else if (id_freeze & !datab_saved[32]) begin
                datab_saved <= #1 {1'b1, from_rfb};
        end
        else if (!id_freeze)
                datab_saved <= #1 33'b0;
 
`ifdef OR1200_RFRAM_TWOPORT
 
//
// Instantiation of register file two-port RAM A
//
or1200_tpram_32x32 rf_a(
        // Port A
        .clk_a(clk),
        .rst_a(rst),
        .ce_a(rf_ena),
        .we_a(1'b0),
        .oe_a(1'b1),
        .addr_a(rf_addra),
        .di_a(32'h0000_0000),
        .do_a(from_rfa),
 
        // Port B
        .clk_b(clk),
        .rst_b(rst),
        .ce_b(rf_we),
        .we_b(rf_we),
        .oe_b(1'b0),
        .addr_b(rf_addrw),
        .di_b(rf_dataw),
        .do_b()
);
 
//
// Instantiation of register file two-port RAM B
//
or1200_tpram_32x32 rf_b(
        // Port A
        .clk_a(clk),
        .rst_a(rst),
        .ce_a(rf_enb),
        .we_a(1'b0),
        .oe_a(1'b1),
        .addr_a(addrb),
        .di_a(32'h0000_0000),
        .do_a(from_rfb),
 
        // Port B
        .clk_b(clk),
        .rst_b(rst),
        .ce_b(rf_we),
        .we_b(rf_we),
        .oe_b(1'b0),
        .addr_b(rf_addrw),
        .di_b(rf_dataw),
        .do_b()
);
 
`else
 
`ifdef OR1200_RFRAM_DUALPORT
 
//
// Instantiation of register file two-port RAM A
//
or1200_dpram_32x32 rf_a(
        // Port A
        .clk_a(clk),
        .rst_a(rst),
        .ce_a(rf_ena),
        .oe_a(1'b1),
        .addr_a(rf_addra),
        .do_a(from_rfa),
 
        // Port B
        .clk_b(clk),
        .rst_b(rst),
        .ce_b(rf_we),
        .we_b(rf_we),
        .addr_b(rf_addrw),
        .di_b(rf_dataw)
);
 
//
// Instantiation of register file two-port RAM B
//
or1200_dpram_32x32 rf_b(
        // Port A
        .clk_a(clk),
        .rst_a(rst),
        .ce_a(rf_enb),
        .oe_a(1'b1),
        .addr_a(addrb),
        .do_a(from_rfb),
 
        // Port B
        .clk_b(clk),
        .rst_b(rst),
        .ce_b(rf_we),
        .we_b(rf_we),
        .addr_b(rf_addrw),
        .di_b(rf_dataw)
);
 
`else
 
`ifdef OR1200_RFRAM_GENERIC
 
//
// Instantiation of generic (flip-flop based) register file
//
or1200_rfram_generic rf_a(
        // Clock and reset
        .clk(clk),
        .rst(rst),
 
        // Port A
        .ce_a(rf_ena),
        .addr_a(rf_addra),
        .do_a(from_rfa),
 
        // Port B
        .ce_b(rf_enb),
        .addr_b(addrb),
        .do_b(from_rfb),
 
        // Port W
        .ce_w(rf_we),
        .we_w(rf_we),
        .addr_w(rf_addrw),
        .di_w(rf_dataw)
);
 
`else
 
//
// RFRAM type not specified
//
initial begin
        $display("Define RFRAM type.");
        $finish;
end
 
`endif
`endif
`endif
 
endmodule

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rf.v] - Blame information for rev 108

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's register file inside CPU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of register file memories ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.2 2002/06/08 16:19:09 lampret`
48			`// Added generic flip-flop based memory macro instantiation.`
49			`//`
50			`// Revision 1.1 2002/01/03 08:16:15 lampret`
51			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
52			`//`
53			`// Revision 1.13 2001/11/20 18:46:15 simons`
54			`// Break point bug fixed`
55			`//`
56			`// Revision 1.12 2001/11/13 10:02:21 lampret`
57			`// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)`
58			`//`
59			`// Revision 1.11 2001/11/12 01:45:40 lampret`
60			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
61			`//`
62			`// Revision 1.10 2001/11/10 03:43:57 lampret`
63			`// Fixed exceptions.`
64			`//`
65			`// Revision 1.9 2001/10/21 17:57:16 lampret`
66			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
67			`//`
68			`// Revision 1.8 2001/10/14 13:12:10 lampret`
69			`// MP3 version.`
70			`//`
71			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
72			`// no message`
73			`//`
74			`// Revision 1.3 2001/08/09 13:39:33 lampret`
75			`// Major clean-up.`
76			`//`
77			`// Revision 1.2 2001/07/22 03:31:54 lampret`
78			`// Fixed RAM's oen bug. Cache bypass under development.`
79			`//`
80			`// Revision 1.1 2001/07/20 00:46:21 lampret`
81			`// Development version of RTL. Libraries are missing.`
82			`//`
83			`//`
84
85			`// synopsys translate_off`
86			`include "timescale.v"
87			`// synopsys translate_on`
88			`include "or1200_defines.v"
89
90			`module or1200_rf(`
91			`// Clock and reset`
92			`clk, rst,`
93
94			`// Write i/f`
95			`supv, wb_freeze, addrw, dataw, we, flushpipe,`
96
97			`// Read i/f`
98			`id_freeze, addra, addrb, dataa, datab, rda, rdb,`
99
100			`// Debug`
101			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
102			`);`
103
104			parameter dw = `OR1200_OPERAND_WIDTH;
105			parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
106
107			`//`
108			`// I/O`
109			`//`
110
111			`//`
112			`// Clock and reset`
113			`//`
114			`input clk;`
115			`input rst;`
116
117			`//`
118			`// Write i/f`
119			`//`
120			`input supv;`
121			`input wb_freeze;`
122			`input [aw-1:0] addrw;`
123			`input [dw-1:0] dataw;`
124			`input we;`
125			`input flushpipe;`
126
127			`//`
128			`// Read i/f`
129			`//`
130			`input id_freeze;`
131			`input [aw-1:0] addra;`
132			`input [aw-1:0] addrb;`
133			`output [dw-1:0] dataa;`
134			`output [dw-1:0] datab;`
135			`input rda;`
136			`input rdb;`
137
138			`//`
139			`// SPR access for debugging purposes`
140			`//`
141			`input spr_cs;`
142			`input spr_write;`
143			`input [31:0] spr_addr;`
144			`input [31:0] spr_dat_i;`
145			`output [31:0] spr_dat_o;`
146
147			`//`
148			`// Internal wires and regs`
149			`//`
150			`wire [dw-1:0] from_rfa;`
151			`wire [dw-1:0] from_rfb;`
152			`reg [dw:0] dataa_saved;`
153			`reg [dw:0] datab_saved;`
154			`wire [aw-1:0] rf_addra;`
155			`wire [aw-1:0] rf_addrw;`
156			`wire [dw-1:0] rf_dataw;`
157			`wire rf_we;`
158			`wire spr_valid;`
159			`wire rf_ena;`
160			`wire rf_enb;`
161			`reg rf_we_allow;`
162
163			`//`
164			`// SPR access is valid when spr_cs is asserted and`
165			`// SPR address matches GPR addresses`
166			`//`
167			assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
168
169			`//`
170			`// SPR data output is always from RF A`
171			`//`
172			`assign spr_dat_o = from_rfa;`
173
174			`//`
175			`// Operand A comes from RF or from saved A register`
176			`//`
177			`assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;`
178
179			`//`
180			`// Operand B comes from RF or from saved B register`
181			`//`
182			`assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;`
183
184			`//`
185			`// RF A read address is either from SPRS or normal from CPU control`
186			`//`
187			`assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;`
188
189			`//`
190			`// RF write address is either from SPRS or normal from CPU control`
191			`//`
192			`assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;`
193
194			`//`
195			`// RF write data is either from SPRS or normal from CPU datapath`
196			`//`
197			`assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;`
198
199			`//`
200			`// RF write enable is either from SPRS or normal from CPU control`
201			`//`
202			`always @(posedge rst or posedge clk)`
203			`if (rst)`
204			`rf_we_allow <= #1 1'b1;`
205			`else if (~wb_freeze)`
206			`rf_we_allow <= #1 ~flushpipe;`
207
208			`assign rf_we = ((spr_valid & spr_write) \| (we & ~wb_freeze)) & rf_we_allow & (supv \| (\|rf_addrw));`
209
210			`//`
211			`// CS RF A asserted when instruction reads operand A and ID stage`
212			`// is not stalled`
213			`//`
214			`assign rf_ena = rda & ~id_freeze \| spr_valid; // probably works with fixed binutils`
215			`// assign rf_ena = 1'b1; // does not work with single-stepping`
216			`//assign rf_ena = ~id_freeze \| spr_valid; // works with broken binutils`
217
218			`//`
219			`// CS RF B asserted when instruction reads operand B and ID stage`
220			`// is not stalled`
221			`//`
222			`assign rf_enb = rdb & ~id_freeze \| spr_valid;`
223			`// assign rf_enb = 1'b1;`
224			`//assign rf_enb = ~id_freeze \| spr_valid; // works with broken binutils`
225
226			`//`
227			`// Stores operand from RF_A into temp reg when pipeline is frozen`
228			`//`
229			`always @(posedge clk or posedge rst)`
230			`if (rst) begin`
231			`dataa_saved <= #1 33'b0;`
232			`end`
233			`else if (id_freeze & !dataa_saved[32]) begin`
234			`dataa_saved <= #1 {1'b1, from_rfa};`
235			`end`
236			`else if (!id_freeze)`
237			`dataa_saved <= #1 33'b0;`
238
239			`//`
240			`// Stores operand from RF_B into temp reg when pipeline is frozen`
241			`//`
242			`always @(posedge clk or posedge rst)`
243			`if (rst) begin`
244			`datab_saved <= #1 33'b0;`
245			`end`
246			`else if (id_freeze & !datab_saved[32]) begin`
247			`datab_saved <= #1 {1'b1, from_rfb};`
248			`end`
249			`else if (!id_freeze)`
250			`datab_saved <= #1 33'b0;`
251
252			`ifdef OR1200_RFRAM_TWOPORT
253
254			`//`
255			`// Instantiation of register file two-port RAM A`
256			`//`
257			`or1200_tpram_32x32 rf_a(`
258			`// Port A`
259			`.clk_a(clk),`
260			`.rst_a(rst),`
261			`.ce_a(rf_ena),`
262			`.we_a(1'b0),`
263			`.oe_a(1'b1),`
264			`.addr_a(rf_addra),`
265			`.di_a(32'h0000_0000),`
266			`.do_a(from_rfa),`
267
268			`// Port B`
269			`.clk_b(clk),`
270			`.rst_b(rst),`
271			`.ce_b(rf_we),`
272			`.we_b(rf_we),`
273			`.oe_b(1'b0),`
274			`.addr_b(rf_addrw),`
275			`.di_b(rf_dataw),`
276			`.do_b()`
277			`);`
278
279			`//`
280			`// Instantiation of register file two-port RAM B`
281			`//`
282			`or1200_tpram_32x32 rf_b(`
283			`// Port A`
284			`.clk_a(clk),`
285			`.rst_a(rst),`
286			`.ce_a(rf_enb),`
287			`.we_a(1'b0),`
288			`.oe_a(1'b1),`
289			`.addr_a(addrb),`
290			`.di_a(32'h0000_0000),`
291			`.do_a(from_rfb),`
292
293			`// Port B`
294			`.clk_b(clk),`
295			`.rst_b(rst),`
296			`.ce_b(rf_we),`
297			`.we_b(rf_we),`
298			`.oe_b(1'b0),`
299			`.addr_b(rf_addrw),`
300			`.di_b(rf_dataw),`
301			`.do_b()`
302			`);`
303
304			`else
305
306			`ifdef OR1200_RFRAM_DUALPORT
307
308			`//`
309			`// Instantiation of register file two-port RAM A`
310			`//`
311			`or1200_dpram_32x32 rf_a(`
312			`// Port A`
313			`.clk_a(clk),`
314			`.rst_a(rst),`
315			`.ce_a(rf_ena),`
316			`.oe_a(1'b1),`
317			`.addr_a(rf_addra),`
318			`.do_a(from_rfa),`
319
320			`// Port B`
321			`.clk_b(clk),`
322			`.rst_b(rst),`
323			`.ce_b(rf_we),`
324			`.we_b(rf_we),`
325			`.addr_b(rf_addrw),`
326			`.di_b(rf_dataw)`
327			`);`
328
329			`//`
330			`// Instantiation of register file two-port RAM B`
331			`//`
332			`or1200_dpram_32x32 rf_b(`
333			`// Port A`
334			`.clk_a(clk),`
335			`.rst_a(rst),`
336			`.ce_a(rf_enb),`
337			`.oe_a(1'b1),`
338			`.addr_a(addrb),`
339			`.do_a(from_rfb),`
340
341			`// Port B`
342			`.clk_b(clk),`
343			`.rst_b(rst),`
344			`.ce_b(rf_we),`
345			`.we_b(rf_we),`
346			`.addr_b(rf_addrw),`
347			`.di_b(rf_dataw)`
348			`);`
349
350			`else
351
352			`ifdef OR1200_RFRAM_GENERIC
353
354			`//`
355			`// Instantiation of generic (flip-flop based) register file`
356			`//`
357			`or1200_rfram_generic rf_a(`
358			`// Clock and reset`
359			`.clk(clk),`
360			`.rst(rst),`
361
362			`// Port A`
363			`.ce_a(rf_ena),`
364			`.addr_a(rf_addra),`
365			`.do_a(from_rfa),`
366
367			`// Port B`
368			`.ce_b(rf_enb),`
369			`.addr_b(addrb),`
370			`.do_b(from_rfb),`
371
372			`// Port W`
373			`.ce_w(rf_we),`
374			`.we_w(rf_we),`
375			`.addr_w(rf_addrw),`
376			`.di_w(rf_dataw)`
377			`);`
378
379			`else
380
381			`//`
382			`// RFRAM type not specified`
383			`//`
384			`initial begin`
385			`$display("Define RFRAM type.");`
386			`$finish;`
387			`end`
388
389			`endif
390			`endif
391			`endif
392
393			`endmodule`