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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rf.v] - Blame information for rev 141

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1 10 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's register file inside CPU                           ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of register file memories                     ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
46 141 marcus.erl
// $Log: or1200_rf.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// Minor update: 
49
// Bugs fixed, coding style changed. 
50
//
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// Revision 1.3  2003/04/07 01:21:56  lampret
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// RFRAM type always need to be defined.
53
//
54 10 unneback
// Revision 1.2  2002/06/08 16:19:09  lampret
55
// Added generic flip-flop based memory macro instantiation.
56
//
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// Revision 1.1  2002/01/03 08:16:15  lampret
58
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
59
//
60
// Revision 1.13  2001/11/20 18:46:15  simons
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// Break point bug fixed
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//
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// Revision 1.12  2001/11/13 10:02:21  lampret
64
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
65
//
66
// Revision 1.11  2001/11/12 01:45:40  lampret
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
68
//
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// Revision 1.10  2001/11/10 03:43:57  lampret
70
// Fixed exceptions.
71
//
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// Revision 1.9  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
74
//
75
// Revision 1.8  2001/10/14 13:12:10  lampret
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// MP3 version.
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//
78
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.3  2001/08/09 13:39:33  lampret
82
// Major clean-up.
83
//
84
// Revision 1.2  2001/07/22 03:31:54  lampret
85
// Fixed RAM's oen bug. Cache bypass under development.
86
//
87
// Revision 1.1  2001/07/20 00:46:21  lampret
88
// Development version of RTL. Libraries are missing.
89
//
90
//
91
 
92
// synopsys translate_off
93
`include "timescale.v"
94
// synopsys translate_on
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`include "or1200_defines.v"
96
 
97
module or1200_rf(
98
        // Clock and reset
99
        clk, rst,
100
 
101
        // Write i/f
102 141 marcus.erl
        cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,
103 10 unneback
 
104
        // Read i/f
105
        id_freeze, addra, addrb, dataa, datab, rda, rdb,
106
 
107
        // Debug
108
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
109
);
110
 
111
parameter dw = `OR1200_OPERAND_WIDTH;
112
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
113
 
114
//
115
// I/O
116
//
117
 
118
//
119
// Clock and reset
120
//
121
input                           clk;
122
input                           rst;
123
 
124
//
125
// Write i/f
126
//
127 141 marcus.erl
input                           cy_we_i;
128
output                          cy_we_o;
129 10 unneback
input                           supv;
130
input                           wb_freeze;
131
input   [aw-1:0]         addrw;
132
input   [dw-1:0]         dataw;
133
input                           we;
134
input                           flushpipe;
135
 
136
//
137
// Read i/f
138
//
139
input                           id_freeze;
140
input   [aw-1:0]         addra;
141
input   [aw-1:0]         addrb;
142
output  [dw-1:0]         dataa;
143
output  [dw-1:0]         datab;
144
input                           rda;
145
input                           rdb;
146
 
147
//
148
// SPR access for debugging purposes
149
//
150
input                           spr_cs;
151
input                           spr_write;
152
input   [31:0]                   spr_addr;
153
input   [31:0]                   spr_dat_i;
154
output  [31:0]                   spr_dat_o;
155
 
156
//
157
// Internal wires and regs
158
//
159
wire    [dw-1:0]         from_rfa;
160
wire    [dw-1:0]         from_rfb;
161
wire    [aw-1:0]         rf_addra;
162
wire    [aw-1:0]         rf_addrw;
163
wire    [dw-1:0]         rf_dataw;
164
wire                            rf_we;
165
wire                            spr_valid;
166
wire                            rf_ena;
167
wire                            rf_enb;
168
reg                             rf_we_allow;
169
 
170
//
171
// SPR access is valid when spr_cs is asserted and
172
// SPR address matches GPR addresses
173
//
174
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
175
 
176
//
177
// SPR data output is always from RF A
178
//
179
assign spr_dat_o = from_rfa;
180
 
181
//
182
// Operand A comes from RF or from saved A register
183
//
184 141 marcus.erl
assign dataa = from_rfa;
185 10 unneback
 
186
//
187
// Operand B comes from RF or from saved B register
188
//
189 141 marcus.erl
assign datab = from_rfb;
190 10 unneback
 
191
//
192
// RF A read address is either from SPRS or normal from CPU control
193
//
194
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
195
 
196
//
197
// RF write address is either from SPRS or normal from CPU control
198
//
199
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
200
 
201
//
202
// RF write data is either from SPRS or normal from CPU datapath
203
//
204
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
205
 
206
//
207
// RF write enable is either from SPRS or normal from CPU control
208
//
209
always @(posedge rst or posedge clk)
210
        if (rst)
211
                rf_we_allow <= #1 1'b1;
212
        else if (~wb_freeze)
213
                rf_we_allow <= #1 ~flushpipe;
214
 
215 141 marcus.erl
//assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
216
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
217
//assign cy_we_o = cy_we_i && rf_we;
218
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
219 10 unneback
 
220
//
221
// CS RF A asserted when instruction reads operand A and ID stage
222
// is not stalled
223
//
224 141 marcus.erl
//assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
225
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write);  // probably works with fixed binutils
226 10 unneback
// assign rf_ena = 1'b1;                        // does not work with single-stepping
227
//assign rf_ena = ~id_freeze | spr_valid;       // works with broken binutils 
228
 
229
//
230
// CS RF B asserted when instruction reads operand B and ID stage
231
// is not stalled
232
//
233 141 marcus.erl
//assign rf_enb = rdb & ~id_freeze | spr_valid;
234
assign rf_enb = rdb & ~id_freeze;
235 10 unneback
// assign rf_enb = 1'b1;
236
//assign rf_enb = ~id_freeze | spr_valid;       // works with broken binutils 
237
 
238
`ifdef OR1200_RFRAM_TWOPORT
239
 
240
//
241
// Instantiation of register file two-port RAM A
242
//
243
or1200_tpram_32x32 rf_a(
244
        // Port A
245
        .clk_a(clk),
246
        .rst_a(rst),
247
        .ce_a(rf_ena),
248
        .we_a(1'b0),
249
        .oe_a(1'b1),
250
        .addr_a(rf_addra),
251
        .di_a(32'h0000_0000),
252
        .do_a(from_rfa),
253
 
254
        // Port B
255
        .clk_b(clk),
256
        .rst_b(rst),
257
        .ce_b(rf_we),
258
        .we_b(rf_we),
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        .oe_b(1'b0),
260
        .addr_b(rf_addrw),
261
        .di_b(rf_dataw),
262
        .do_b()
263
);
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265
//
266
// Instantiation of register file two-port RAM B
267
//
268
or1200_tpram_32x32 rf_b(
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        // Port A
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        .clk_a(clk),
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        .rst_a(rst),
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        .ce_a(rf_enb),
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        .we_a(1'b0),
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        .oe_a(1'b1),
275
        .addr_a(addrb),
276
        .di_a(32'h0000_0000),
277
        .do_a(from_rfb),
278
 
279
        // Port B
280
        .clk_b(clk),
281
        .rst_b(rst),
282
        .ce_b(rf_we),
283
        .we_b(rf_we),
284
        .oe_b(1'b0),
285
        .addr_b(rf_addrw),
286
        .di_b(rf_dataw),
287
        .do_b()
288
);
289
 
290
`else
291
 
292
`ifdef OR1200_RFRAM_DUALPORT
293
 
294
//
295
// Instantiation of register file two-port RAM A
296
//
297 141 marcus.erl
   or1200_dpram #
298
     (
299
      .aw(5),
300
      .dw(32)
301
      )
302
   rf_a
303
     (
304
      // Port A
305
      .clk_a(clk),
306
      .ce_a(rf_ena),
307
      .addr_a(rf_addra),
308
      .do_a(from_rfa),
309
 
310
      // Port B
311
      .clk_b(clk),
312
      .ce_b(rf_we),
313
      .we_b(rf_we),
314
      .addr_b(rf_addrw),
315
      .di_b(rf_dataw)
316
      );
317 10 unneback
 
318 141 marcus.erl
   //
319
   // Instantiation of register file two-port RAM B
320
   //
321
   or1200_dpram #
322
     (
323
      .aw(5),
324
      .dw(32)
325
      )
326
   rf_b
327
     (
328
      // Port A
329
      .clk_a(clk),
330
      .ce_a(rf_enb),
331
      .addr_a(addrb),
332
      .do_a(from_rfb),
333
 
334
      // Port B
335
      .clk_b(clk),
336
      .ce_b(rf_we),
337
      .we_b(rf_we),
338
      .addr_b(rf_addrw),
339
      .di_b(rf_dataw)
340
      );
341
 
342 10 unneback
`else
343
 
344
`ifdef OR1200_RFRAM_GENERIC
345
 
346
//
347
// Instantiation of generic (flip-flop based) register file
348
//
349
or1200_rfram_generic rf_a(
350
        // Clock and reset
351
        .clk(clk),
352
        .rst(rst),
353
 
354
        // Port A
355
        .ce_a(rf_ena),
356
        .addr_a(rf_addra),
357
        .do_a(from_rfa),
358
 
359
        // Port B
360
        .ce_b(rf_enb),
361
        .addr_b(addrb),
362
        .do_b(from_rfb),
363
 
364
        // Port W
365
        .ce_w(rf_we),
366
        .we_w(rf_we),
367
        .addr_w(rf_addrw),
368
        .di_w(rf_dataw)
369
);
370
 
371
`else
372
 
373
//
374
// RFRAM type not specified
375
//
376
initial begin
377
        $display("Define RFRAM type.");
378
        $finish;
379
end
380
 
381
`endif
382
`endif
383
`endif
384
 
385
endmodule

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