OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rf.v] - Blame information for rev 186

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's register file inside CPU                           ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 186 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Instantiation of register file memories                     ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44 141 marcus.erl
// $Log: or1200_rf.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Minor update: 
47
// Bugs fixed, coding style changed. 
48
//
49 10 unneback
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55
module or1200_rf(
56
        // Clock and reset
57
        clk, rst,
58
 
59
        // Write i/f
60 141 marcus.erl
        cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,
61 10 unneback
 
62
        // Read i/f
63
        id_freeze, addra, addrb, dataa, datab, rda, rdb,
64
 
65
        // Debug
66
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
67
);
68
 
69
parameter dw = `OR1200_OPERAND_WIDTH;
70
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
71
 
72
//
73
// I/O
74
//
75
 
76
//
77
// Clock and reset
78
//
79
input                           clk;
80
input                           rst;
81
 
82
//
83
// Write i/f
84
//
85 141 marcus.erl
input                           cy_we_i;
86
output                          cy_we_o;
87 10 unneback
input                           supv;
88
input                           wb_freeze;
89
input   [aw-1:0]         addrw;
90
input   [dw-1:0]         dataw;
91
input                           we;
92
input                           flushpipe;
93
 
94
//
95
// Read i/f
96
//
97
input                           id_freeze;
98
input   [aw-1:0]         addra;
99
input   [aw-1:0]         addrb;
100
output  [dw-1:0]         dataa;
101
output  [dw-1:0]         datab;
102
input                           rda;
103
input                           rdb;
104
 
105
//
106
// SPR access for debugging purposes
107
//
108
input                           spr_cs;
109
input                           spr_write;
110
input   [31:0]                   spr_addr;
111
input   [31:0]                   spr_dat_i;
112
output  [31:0]                   spr_dat_o;
113
 
114
//
115
// Internal wires and regs
116
//
117
wire    [dw-1:0]         from_rfa;
118
wire    [dw-1:0]         from_rfb;
119
wire    [aw-1:0]         rf_addra;
120
wire    [aw-1:0]         rf_addrw;
121
wire    [dw-1:0]         rf_dataw;
122
wire                            rf_we;
123
wire                            spr_valid;
124
wire                            rf_ena;
125
wire                            rf_enb;
126
reg                             rf_we_allow;
127
 
128
//
129
// SPR access is valid when spr_cs is asserted and
130
// SPR address matches GPR addresses
131
//
132
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
133
 
134
//
135
// SPR data output is always from RF A
136
//
137
assign spr_dat_o = from_rfa;
138
 
139
//
140
// Operand A comes from RF or from saved A register
141
//
142 141 marcus.erl
assign dataa = from_rfa;
143 10 unneback
 
144
//
145
// Operand B comes from RF or from saved B register
146
//
147 141 marcus.erl
assign datab = from_rfb;
148 10 unneback
 
149
//
150
// RF A read address is either from SPRS or normal from CPU control
151
//
152
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
153
 
154
//
155
// RF write address is either from SPRS or normal from CPU control
156
//
157
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
158
 
159
//
160
// RF write data is either from SPRS or normal from CPU datapath
161
//
162
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
163
 
164
//
165
// RF write enable is either from SPRS or normal from CPU control
166
//
167
always @(posedge rst or posedge clk)
168
        if (rst)
169
                rf_we_allow <= #1 1'b1;
170
        else if (~wb_freeze)
171
                rf_we_allow <= #1 ~flushpipe;
172
 
173 141 marcus.erl
//assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
174
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
175
//assign cy_we_o = cy_we_i && rf_we;
176
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
177 10 unneback
 
178
//
179
// CS RF A asserted when instruction reads operand A and ID stage
180
// is not stalled
181
//
182 141 marcus.erl
//assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
183
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write);  // probably works with fixed binutils
184 10 unneback
// assign rf_ena = 1'b1;                        // does not work with single-stepping
185
//assign rf_ena = ~id_freeze | spr_valid;       // works with broken binutils 
186
 
187
//
188
// CS RF B asserted when instruction reads operand B and ID stage
189
// is not stalled
190
//
191 141 marcus.erl
//assign rf_enb = rdb & ~id_freeze | spr_valid;
192
assign rf_enb = rdb & ~id_freeze;
193 10 unneback
// assign rf_enb = 1'b1;
194
//assign rf_enb = ~id_freeze | spr_valid;       // works with broken binutils 
195
 
196
`ifdef OR1200_RFRAM_TWOPORT
197
 
198
//
199
// Instantiation of register file two-port RAM A
200
//
201
or1200_tpram_32x32 rf_a(
202
        // Port A
203
        .clk_a(clk),
204
        .rst_a(rst),
205
        .ce_a(rf_ena),
206
        .we_a(1'b0),
207
        .oe_a(1'b1),
208
        .addr_a(rf_addra),
209
        .di_a(32'h0000_0000),
210
        .do_a(from_rfa),
211
 
212
        // Port B
213
        .clk_b(clk),
214
        .rst_b(rst),
215
        .ce_b(rf_we),
216
        .we_b(rf_we),
217
        .oe_b(1'b0),
218
        .addr_b(rf_addrw),
219
        .di_b(rf_dataw),
220
        .do_b()
221
);
222
 
223
//
224
// Instantiation of register file two-port RAM B
225
//
226
or1200_tpram_32x32 rf_b(
227
        // Port A
228
        .clk_a(clk),
229
        .rst_a(rst),
230
        .ce_a(rf_enb),
231
        .we_a(1'b0),
232
        .oe_a(1'b1),
233
        .addr_a(addrb),
234
        .di_a(32'h0000_0000),
235
        .do_a(from_rfb),
236
 
237
        // Port B
238
        .clk_b(clk),
239
        .rst_b(rst),
240
        .ce_b(rf_we),
241
        .we_b(rf_we),
242
        .oe_b(1'b0),
243
        .addr_b(rf_addrw),
244
        .di_b(rf_dataw),
245
        .do_b()
246
);
247
 
248
`else
249
 
250
`ifdef OR1200_RFRAM_DUALPORT
251
 
252
//
253
// Instantiation of register file two-port RAM A
254
//
255 141 marcus.erl
   or1200_dpram #
256
     (
257
      .aw(5),
258
      .dw(32)
259
      )
260
   rf_a
261
     (
262
      // Port A
263
      .clk_a(clk),
264
      .ce_a(rf_ena),
265
      .addr_a(rf_addra),
266
      .do_a(from_rfa),
267
 
268
      // Port B
269
      .clk_b(clk),
270
      .ce_b(rf_we),
271
      .we_b(rf_we),
272
      .addr_b(rf_addrw),
273
      .di_b(rf_dataw)
274
      );
275 10 unneback
 
276 141 marcus.erl
   //
277
   // Instantiation of register file two-port RAM B
278
   //
279
   or1200_dpram #
280
     (
281
      .aw(5),
282
      .dw(32)
283
      )
284
   rf_b
285
     (
286
      // Port A
287
      .clk_a(clk),
288
      .ce_a(rf_enb),
289
      .addr_a(addrb),
290
      .do_a(from_rfb),
291
 
292
      // Port B
293
      .clk_b(clk),
294
      .ce_b(rf_we),
295
      .we_b(rf_we),
296
      .addr_b(rf_addrw),
297
      .di_b(rf_dataw)
298
      );
299
 
300 10 unneback
`else
301
 
302
`ifdef OR1200_RFRAM_GENERIC
303
 
304
//
305
// Instantiation of generic (flip-flop based) register file
306
//
307
or1200_rfram_generic rf_a(
308
        // Clock and reset
309
        .clk(clk),
310
        .rst(rst),
311
 
312
        // Port A
313
        .ce_a(rf_ena),
314
        .addr_a(rf_addra),
315
        .do_a(from_rfa),
316
 
317
        // Port B
318
        .ce_b(rf_enb),
319
        .addr_b(addrb),
320
        .do_b(from_rfb),
321
 
322
        // Port W
323
        .ce_w(rf_we),
324
        .we_w(rf_we),
325
        .addr_w(rf_addrw),
326
        .di_w(rf_dataw)
327
);
328
 
329
`else
330
 
331
//
332
// RFRAM type not specified
333
//
334
initial begin
335
        $display("Define RFRAM type.");
336
        $finish;
337
end
338
 
339
`endif
340
`endif
341
`endif
342
 
343
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.