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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rf.v] - Blame information for rev 358

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1 10 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's register file inside CPU                           ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
6 186 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
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////  Description                                                 ////
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////  Instantiation of register file memories                     ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
44 141 marcus.erl
// $Log: or1200_rf.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// Minor update: 
47
// Bugs fixed, coding style changed. 
48
//
49 10 unneback
 
50
// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
54
 
55
module or1200_rf(
56
        // Clock and reset
57
        clk, rst,
58
 
59
        // Write i/f
60 141 marcus.erl
        cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,
61 10 unneback
 
62
        // Read i/f
63
        id_freeze, addra, addrb, dataa, datab, rda, rdb,
64
 
65
        // Debug
66 258 julius
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, du_read
67 10 unneback
);
68
 
69
parameter dw = `OR1200_OPERAND_WIDTH;
70
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
71
 
72
//
73
// I/O
74
//
75
 
76
//
77
// Clock and reset
78
//
79
input                           clk;
80
input                           rst;
81
 
82
//
83
// Write i/f
84
//
85 141 marcus.erl
input                           cy_we_i;
86
output                          cy_we_o;
87 10 unneback
input                           supv;
88
input                           wb_freeze;
89
input   [aw-1:0]         addrw;
90
input   [dw-1:0]         dataw;
91
input                           we;
92
input                           flushpipe;
93
 
94
//
95
// Read i/f
96
//
97
input                           id_freeze;
98
input   [aw-1:0]         addra;
99
input   [aw-1:0]         addrb;
100
output  [dw-1:0]         dataa;
101
output  [dw-1:0]         datab;
102
input                           rda;
103
input                           rdb;
104
 
105
//
106
// SPR access for debugging purposes
107
//
108
input                           spr_cs;
109
input                           spr_write;
110
input   [31:0]                   spr_addr;
111
input   [31:0]                   spr_dat_i;
112
output  [31:0]                   spr_dat_o;
113 258 julius
input                           du_read;
114
 
115 10 unneback
//
116
// Internal wires and regs
117
//
118
wire    [dw-1:0]         from_rfa;
119
wire    [dw-1:0]         from_rfb;
120
wire    [aw-1:0]         rf_addra;
121
wire    [aw-1:0]         rf_addrw;
122
wire    [dw-1:0]         rf_dataw;
123
wire                            rf_we;
124
wire                            spr_valid;
125
wire                            rf_ena;
126
wire                            rf_enb;
127
reg                             rf_we_allow;
128
 
129 258 julius
   // Logic to restore output on RFA after debug unit has read out via SPR if.
130
   // Problem was that the incorrect output would be on RFA after debug unit
131
   // had read out  - this is bad if that output is relied upon by execute
132
   // stage for next instruction. We simply save the last address for rf A and
133
   // and re-read it whenever the SPR select goes low, so we must remember
134
   // the last address and generate a signal for falling edge of SPR cs.
135
   // -- Julius
136
 
137
   // Detect falling edge of SPR select 
138
   reg                          spr_du_cs;
139
   wire                         spr_cs_fe;
140
   // Track RF A's address each time it's enabled
141
   reg  [aw-1:0]         addra_last;
142
 
143
 
144
   always @(posedge clk)
145
     if (rf_ena & !(spr_cs_fe | (du_read & spr_cs)))
146
       addra_last <= addra;
147
 
148
   always @(posedge clk)
149
     spr_du_cs <= spr_cs & du_read;
150
 
151
   assign spr_cs_fe = spr_du_cs & !(spr_cs & du_read);
152
 
153
 
154 10 unneback
//
155
// SPR access is valid when spr_cs is asserted and
156
// SPR address matches GPR addresses
157
//
158
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
159
 
160
//
161
// SPR data output is always from RF A
162
//
163
assign spr_dat_o = from_rfa;
164
 
165
//
166
// Operand A comes from RF or from saved A register
167
//
168 141 marcus.erl
assign dataa = from_rfa;
169 10 unneback
 
170
//
171
// Operand B comes from RF or from saved B register
172
//
173 141 marcus.erl
assign datab = from_rfb;
174 10 unneback
 
175
//
176
// RF A read address is either from SPRS or normal from CPU control
177
//
178 258 julius
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] :
179
                  spr_cs_fe ? addra_last : addra;
180 10 unneback
 
181
//
182
// RF write address is either from SPRS or normal from CPU control
183
//
184
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
185
 
186
//
187
// RF write data is either from SPRS or normal from CPU datapath
188
//
189
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
190
 
191
//
192
// RF write enable is either from SPRS or normal from CPU control
193
//
194 358 julius
always @(`OR1200_RST_EVENT rst or posedge clk)
195
        if (rst == `OR1200_RST_VALUE)
196 258 julius
                rf_we_allow <=  1'b1;
197 10 unneback
        else if (~wb_freeze)
198 258 julius
                rf_we_allow <=  ~flushpipe;
199 10 unneback
 
200 141 marcus.erl
//assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
201
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
202
//assign cy_we_o = cy_we_i && rf_we;
203
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
204 258 julius
 
205
 
206 10 unneback
//
207
// CS RF A asserted when instruction reads operand A and ID stage
208
// is not stalled
209
//
210 141 marcus.erl
//assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
211 258 julius
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;      // probably works with fixed binutils
212 10 unneback
// assign rf_ena = 1'b1;                        // does not work with single-stepping
213
//assign rf_ena = ~id_freeze | spr_valid;       // works with broken binutils 
214
 
215
//
216
// CS RF B asserted when instruction reads operand B and ID stage
217
// is not stalled
218
//
219 141 marcus.erl
//assign rf_enb = rdb & ~id_freeze | spr_valid;
220
assign rf_enb = rdb & ~id_freeze;
221 10 unneback
// assign rf_enb = 1'b1;
222
//assign rf_enb = ~id_freeze | spr_valid;       // works with broken binutils 
223
 
224
`ifdef OR1200_RFRAM_TWOPORT
225
 
226
//
227
// Instantiation of register file two-port RAM A
228
//
229
or1200_tpram_32x32 rf_a(
230
        // Port A
231
        .clk_a(clk),
232
        .rst_a(rst),
233
        .ce_a(rf_ena),
234
        .we_a(1'b0),
235
        .oe_a(1'b1),
236
        .addr_a(rf_addra),
237
        .di_a(32'h0000_0000),
238
        .do_a(from_rfa),
239
 
240
        // Port B
241
        .clk_b(clk),
242
        .rst_b(rst),
243
        .ce_b(rf_we),
244
        .we_b(rf_we),
245
        .oe_b(1'b0),
246
        .addr_b(rf_addrw),
247
        .di_b(rf_dataw),
248
        .do_b()
249
);
250
 
251
//
252
// Instantiation of register file two-port RAM B
253
//
254
or1200_tpram_32x32 rf_b(
255
        // Port A
256
        .clk_a(clk),
257
        .rst_a(rst),
258
        .ce_a(rf_enb),
259
        .we_a(1'b0),
260
        .oe_a(1'b1),
261
        .addr_a(addrb),
262
        .di_a(32'h0000_0000),
263
        .do_a(from_rfb),
264
 
265
        // Port B
266
        .clk_b(clk),
267
        .rst_b(rst),
268
        .ce_b(rf_we),
269
        .we_b(rf_we),
270
        .oe_b(1'b0),
271
        .addr_b(rf_addrw),
272
        .di_b(rf_dataw),
273
        .do_b()
274
);
275
 
276
`else
277
 
278
`ifdef OR1200_RFRAM_DUALPORT
279
 
280
//
281
// Instantiation of register file two-port RAM A
282
//
283 141 marcus.erl
   or1200_dpram #
284
     (
285
      .aw(5),
286
      .dw(32)
287
      )
288
   rf_a
289
     (
290
      // Port A
291
      .clk_a(clk),
292
      .ce_a(rf_ena),
293
      .addr_a(rf_addra),
294
      .do_a(from_rfa),
295
 
296
      // Port B
297
      .clk_b(clk),
298
      .ce_b(rf_we),
299
      .we_b(rf_we),
300
      .addr_b(rf_addrw),
301
      .di_b(rf_dataw)
302
      );
303 10 unneback
 
304 141 marcus.erl
   //
305
   // Instantiation of register file two-port RAM B
306
   //
307
   or1200_dpram #
308
     (
309
      .aw(5),
310
      .dw(32)
311
      )
312
   rf_b
313
     (
314
      // Port A
315
      .clk_a(clk),
316
      .ce_a(rf_enb),
317
      .addr_a(addrb),
318
      .do_a(from_rfb),
319
 
320
      // Port B
321
      .clk_b(clk),
322
      .ce_b(rf_we),
323
      .we_b(rf_we),
324
      .addr_b(rf_addrw),
325
      .di_b(rf_dataw)
326
      );
327
 
328 10 unneback
`else
329
 
330
`ifdef OR1200_RFRAM_GENERIC
331
 
332
//
333
// Instantiation of generic (flip-flop based) register file
334
//
335
or1200_rfram_generic rf_a(
336
        // Clock and reset
337
        .clk(clk),
338
        .rst(rst),
339
 
340
        // Port A
341
        .ce_a(rf_ena),
342
        .addr_a(rf_addra),
343
        .do_a(from_rfa),
344
 
345
        // Port B
346
        .ce_b(rf_enb),
347
        .addr_b(addrb),
348
        .do_b(from_rfb),
349
 
350
        // Port W
351
        .ce_w(rf_we),
352
        .we_w(rf_we),
353
        .addr_w(rf_addrw),
354
        .di_w(rf_dataw)
355
);
356
 
357
`else
358
 
359
//
360
// RFRAM type not specified
361
//
362
initial begin
363
        $display("Define RFRAM type.");
364
        $finish;
365
end
366
 
367
`endif
368
`endif
369
`endif
370
 
371
endmodule

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