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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rfram_generic.v] - Blame information for rev 358

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1 10 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's register file generic memory                       ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Generic (flip-flop based) register file memory              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - nothing                                                  ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
45 141 marcus.erl
//
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// $Log: or1200_rfram_generic.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// Minor update: 
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// Defines added, coding style changed. 
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//
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// Revision 1.3  2004/06/08 18:16:32  lampret
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// GPR0 hardwired to zero.
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//
54 10 unneback
// Revision 1.2  2002/09/03 22:28:21  lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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// Revision 1.1  2002/06/08 16:23:30  lampret
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// Generic flip-flop based memory macro for register file.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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67
module or1200_rfram_generic(
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        // Clock and reset
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        clk, rst,
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71
        // Port A
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        ce_a, addr_a, do_a,
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74
        // Port B
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        ce_b, addr_b, do_b,
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77
        // Port W
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        ce_w, we_w, addr_w, di_w
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);
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81
parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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84
//
85
// I/O
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//
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88
//
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// Clock and reset
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//
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input                           clk;
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input                           rst;
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94
//
95
// Port A
96
//
97
input                           ce_a;
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input   [aw-1:0]         addr_a;
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output  [dw-1:0]         do_a;
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101
//
102
// Port B
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//
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input                           ce_b;
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input   [aw-1:0]         addr_b;
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output  [dw-1:0]         do_b;
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108
//
109
// Port W
110
//
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input                           ce_w;
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input                           we_w;
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input   [aw-1:0]         addr_w;
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input   [dw-1:0]         di_w;
115
 
116
//
117
// Internal wires and regs
118
//
119
reg     [aw-1:0]         intaddr_a;
120
reg     [aw-1:0]         intaddr_b;
121 141 marcus.erl
`ifdef OR1200_RFRAM_16REG
122
reg     [16*dw-1:0]              mem;
123
`else
124 10 unneback
reg     [32*dw-1:0]              mem;
125 141 marcus.erl
`endif
126 10 unneback
reg     [dw-1:0]         do_a;
127
reg     [dw-1:0]         do_b;
128
 
129 141 marcus.erl
   // Function to access GPRs (for use by Verilator). No need to hide this one
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   // from the simulator, since it has an input (as required by IEEE 1364-2001).
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   function [31:0] get_gpr;
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      // verilator public
133
      input [aw-1:0]             gpr_no;
134
 
135
      get_gpr = { mem[gpr_no*32 + 31], mem[gpr_no*32 + 30],
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                  mem[gpr_no*32 + 29], mem[gpr_no*32 + 28],
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                  mem[gpr_no*32 + 27], mem[gpr_no*32 + 26],
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                  mem[gpr_no*32 + 25], mem[gpr_no*32 + 24],
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                  mem[gpr_no*32 + 23], mem[gpr_no*32 + 22],
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                  mem[gpr_no*32 + 21], mem[gpr_no*32 + 20],
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                  mem[gpr_no*32 + 19], mem[gpr_no*32 + 18],
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                  mem[gpr_no*32 + 17], mem[gpr_no*32 + 16],
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                  mem[gpr_no*32 + 15], mem[gpr_no*32 + 14],
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                  mem[gpr_no*32 + 13], mem[gpr_no*32 + 12],
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                  mem[gpr_no*32 + 11], mem[gpr_no*32 + 10],
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                  mem[gpr_no*32 +  9], mem[gpr_no*32 +  8],
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                  mem[gpr_no*32 +  7], mem[gpr_no*32 +  6],
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                  mem[gpr_no*32 +  5], mem[gpr_no*32 +  4],
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                  mem[gpr_no*32 +  3], mem[gpr_no*32 +  2],
150
                  mem[gpr_no*32 +  1], mem[gpr_no*32 +  0] };
151
 
152
   endfunction // get_gpr
153
 
154 10 unneback
//
155
// Write port
156
//
157 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
158
        if (rst == `OR1200_RST_VALUE) begin
159 258 julius
                mem <=  {512'h0, 512'h0};
160 10 unneback
        end
161
        else if (ce_w & we_w)
162
                case (addr_w)   // synopsys parallel_case
163 258 julius
                        5'd01: mem[32*1+31:32*1] <=  di_w;
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                        5'd02: mem[32*2+31:32*2] <=  di_w;
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                        5'd03: mem[32*3+31:32*3] <=  di_w;
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                        5'd04: mem[32*4+31:32*4] <=  di_w;
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                        5'd05: mem[32*5+31:32*5] <=  di_w;
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                        5'd06: mem[32*6+31:32*6] <=  di_w;
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                        5'd07: mem[32*7+31:32*7] <=  di_w;
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                        5'd08: mem[32*8+31:32*8] <=  di_w;
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                        5'd09: mem[32*9+31:32*9] <=  di_w;
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                        5'd10: mem[32*10+31:32*10] <=  di_w;
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                        5'd11: mem[32*11+31:32*11] <=  di_w;
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                        5'd12: mem[32*12+31:32*12] <=  di_w;
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                        5'd13: mem[32*13+31:32*13] <=  di_w;
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                        5'd14: mem[32*14+31:32*14] <=  di_w;
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                        5'd15: mem[32*15+31:32*15] <=  di_w;
178 141 marcus.erl
`ifdef OR1200_RFRAM_16REG
179
`else
180 258 julius
                        5'd16: mem[32*16+31:32*16] <=  di_w;
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                        5'd17: mem[32*17+31:32*17] <=  di_w;
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                        5'd18: mem[32*18+31:32*18] <=  di_w;
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                        5'd19: mem[32*19+31:32*19] <=  di_w;
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                        5'd20: mem[32*20+31:32*20] <=  di_w;
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                        5'd21: mem[32*21+31:32*21] <=  di_w;
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                        5'd22: mem[32*22+31:32*22] <=  di_w;
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                        5'd23: mem[32*23+31:32*23] <=  di_w;
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                        5'd24: mem[32*24+31:32*24] <=  di_w;
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                        5'd25: mem[32*25+31:32*25] <=  di_w;
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                        5'd26: mem[32*26+31:32*26] <=  di_w;
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                        5'd27: mem[32*27+31:32*27] <=  di_w;
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                        5'd28: mem[32*28+31:32*28] <=  di_w;
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                        5'd29: mem[32*29+31:32*29] <=  di_w;
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                        5'd30: mem[32*30+31:32*30] <=  di_w;
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                        5'd31: mem[32*31+31:32*31] <=  di_w;
196 141 marcus.erl
`endif
197 258 julius
                        default: mem[32*0+31:32*0] <=  32'h0000_0000;
198 10 unneback
                endcase
199
 
200
//
201
// Read port A
202
//
203 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
204
        if (rst == `OR1200_RST_VALUE) begin
205 258 julius
                intaddr_a <=  5'h00;
206 10 unneback
        end
207
        else if (ce_a)
208 258 julius
                intaddr_a <=  addr_a;
209 10 unneback
 
210
always @(mem or intaddr_a)
211
        case (intaddr_a)        // synopsys parallel_case
212
                5'd01: do_a = mem[32*1+31:32*1];
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                5'd02: do_a = mem[32*2+31:32*2];
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                5'd03: do_a = mem[32*3+31:32*3];
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                5'd04: do_a = mem[32*4+31:32*4];
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                5'd05: do_a = mem[32*5+31:32*5];
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                5'd06: do_a = mem[32*6+31:32*6];
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                5'd07: do_a = mem[32*7+31:32*7];
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                5'd08: do_a = mem[32*8+31:32*8];
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                5'd09: do_a = mem[32*9+31:32*9];
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                5'd10: do_a = mem[32*10+31:32*10];
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                5'd11: do_a = mem[32*11+31:32*11];
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                5'd12: do_a = mem[32*12+31:32*12];
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                5'd13: do_a = mem[32*13+31:32*13];
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                5'd14: do_a = mem[32*14+31:32*14];
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                5'd15: do_a = mem[32*15+31:32*15];
227 141 marcus.erl
`ifdef OR1200_RFRAM_16REG
228
`else
229 10 unneback
                5'd16: do_a = mem[32*16+31:32*16];
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                5'd17: do_a = mem[32*17+31:32*17];
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                5'd18: do_a = mem[32*18+31:32*18];
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                5'd19: do_a = mem[32*19+31:32*19];
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                5'd20: do_a = mem[32*20+31:32*20];
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                5'd21: do_a = mem[32*21+31:32*21];
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                5'd22: do_a = mem[32*22+31:32*22];
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                5'd23: do_a = mem[32*23+31:32*23];
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                5'd24: do_a = mem[32*24+31:32*24];
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                5'd25: do_a = mem[32*25+31:32*25];
239
                5'd26: do_a = mem[32*26+31:32*26];
240
                5'd27: do_a = mem[32*27+31:32*27];
241
                5'd28: do_a = mem[32*28+31:32*28];
242
                5'd29: do_a = mem[32*29+31:32*29];
243
                5'd30: do_a = mem[32*30+31:32*30];
244 141 marcus.erl
                5'd31: do_a = mem[32*31+31:32*31];
245
`endif
246
                default: do_a = 32'h0000_0000;
247 10 unneback
        endcase
248
 
249
//
250
// Read port B
251
//
252 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
253
        if (rst == `OR1200_RST_VALUE) begin
254 258 julius
                intaddr_b <=  5'h00;
255 10 unneback
        end
256
        else if (ce_b)
257 258 julius
                intaddr_b <=  addr_b;
258 10 unneback
 
259
always @(mem or intaddr_b)
260
        case (intaddr_b)        // synopsys parallel_case
261
                5'd01: do_b = mem[32*1+31:32*1];
262
                5'd02: do_b = mem[32*2+31:32*2];
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                5'd03: do_b = mem[32*3+31:32*3];
264
                5'd04: do_b = mem[32*4+31:32*4];
265
                5'd05: do_b = mem[32*5+31:32*5];
266
                5'd06: do_b = mem[32*6+31:32*6];
267
                5'd07: do_b = mem[32*7+31:32*7];
268
                5'd08: do_b = mem[32*8+31:32*8];
269
                5'd09: do_b = mem[32*9+31:32*9];
270
                5'd10: do_b = mem[32*10+31:32*10];
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                5'd11: do_b = mem[32*11+31:32*11];
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                5'd12: do_b = mem[32*12+31:32*12];
273
                5'd13: do_b = mem[32*13+31:32*13];
274
                5'd14: do_b = mem[32*14+31:32*14];
275
                5'd15: do_b = mem[32*15+31:32*15];
276 141 marcus.erl
`ifdef OR1200_RFRAM_16REG
277
`else
278 10 unneback
                5'd16: do_b = mem[32*16+31:32*16];
279
                5'd17: do_b = mem[32*17+31:32*17];
280
                5'd18: do_b = mem[32*18+31:32*18];
281
                5'd19: do_b = mem[32*19+31:32*19];
282
                5'd20: do_b = mem[32*20+31:32*20];
283
                5'd21: do_b = mem[32*21+31:32*21];
284
                5'd22: do_b = mem[32*22+31:32*22];
285
                5'd23: do_b = mem[32*23+31:32*23];
286
                5'd24: do_b = mem[32*24+31:32*24];
287
                5'd25: do_b = mem[32*25+31:32*25];
288
                5'd26: do_b = mem[32*26+31:32*26];
289
                5'd27: do_b = mem[32*27+31:32*27];
290
                5'd28: do_b = mem[32*28+31:32*28];
291
                5'd29: do_b = mem[32*29+31:32*29];
292
                5'd30: do_b = mem[32*30+31:32*30];
293 141 marcus.erl
                5'd31: do_b = mem[32*31+31:32*31];
294
`endif
295
                default: do_b = 32'h0000_0000;
296 10 unneback
        endcase
297
 
298
endmodule

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