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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rfram_generic.v] - Blame information for rev 813

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1 10 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's register file generic memory                       ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Generic (flip-flop based) register file memory              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - nothing                                                  ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45 141 marcus.erl
//
46
// $Log: or1200_rfram_generic.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// Minor update: 
49
// Defines added, coding style changed. 
50
//
51
// Revision 1.3  2004/06/08 18:16:32  lampret
52
// GPR0 hardwired to zero.
53
//
54 10 unneback
// Revision 1.2  2002/09/03 22:28:21  lampret
55
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
56
//
57
// Revision 1.1  2002/06/08 16:23:30  lampret
58
// Generic flip-flop based memory macro for register file.
59
//
60
//
61
 
62
// synopsys translate_off
63
`include "timescale.v"
64
// synopsys translate_on
65
`include "or1200_defines.v"
66
 
67
module or1200_rfram_generic(
68
        // Clock and reset
69
        clk, rst,
70
 
71
        // Port A
72
        ce_a, addr_a, do_a,
73
 
74
        // Port B
75
        ce_b, addr_b, do_b,
76
 
77
        // Port W
78
        ce_w, we_w, addr_w, di_w
79
);
80
 
81
parameter dw = `OR1200_OPERAND_WIDTH;
82
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
83
 
84
//
85
// I/O
86
//
87
 
88
//
89
// Clock and reset
90
//
91
input                           clk;
92
input                           rst;
93
 
94
//
95
// Port A
96
//
97
input                           ce_a;
98
input   [aw-1:0]         addr_a;
99
output  [dw-1:0]         do_a;
100
 
101
//
102
// Port B
103
//
104
input                           ce_b;
105
input   [aw-1:0]         addr_b;
106
output  [dw-1:0]         do_b;
107
 
108
//
109
// Port W
110
//
111
input                           ce_w;
112
input                           we_w;
113
input   [aw-1:0]         addr_w;
114
input   [dw-1:0]         di_w;
115
 
116
//
117
// Internal wires and regs
118
//
119
reg     [aw-1:0]         intaddr_a;
120
reg     [aw-1:0]         intaddr_b;
121 141 marcus.erl
`ifdef OR1200_RFRAM_16REG
122
reg     [16*dw-1:0]              mem;
123
`else
124 10 unneback
reg     [32*dw-1:0]              mem;
125 141 marcus.erl
`endif
126 10 unneback
reg     [dw-1:0]         do_a;
127
reg     [dw-1:0]         do_b;
128
 
129 481 julius
`ifdef verilator
130 141 marcus.erl
   // Function to access GPRs (for use by Verilator). No need to hide this one
131
   // from the simulator, since it has an input (as required by IEEE 1364-2001).
132
   function [31:0] get_gpr;
133
      // verilator public
134
      input [aw-1:0]             gpr_no;
135
 
136
      get_gpr = { mem[gpr_no*32 + 31], mem[gpr_no*32 + 30],
137
                  mem[gpr_no*32 + 29], mem[gpr_no*32 + 28],
138
                  mem[gpr_no*32 + 27], mem[gpr_no*32 + 26],
139
                  mem[gpr_no*32 + 25], mem[gpr_no*32 + 24],
140
                  mem[gpr_no*32 + 23], mem[gpr_no*32 + 22],
141
                  mem[gpr_no*32 + 21], mem[gpr_no*32 + 20],
142
                  mem[gpr_no*32 + 19], mem[gpr_no*32 + 18],
143
                  mem[gpr_no*32 + 17], mem[gpr_no*32 + 16],
144
                  mem[gpr_no*32 + 15], mem[gpr_no*32 + 14],
145
                  mem[gpr_no*32 + 13], mem[gpr_no*32 + 12],
146
                  mem[gpr_no*32 + 11], mem[gpr_no*32 + 10],
147
                  mem[gpr_no*32 +  9], mem[gpr_no*32 +  8],
148
                  mem[gpr_no*32 +  7], mem[gpr_no*32 +  6],
149
                  mem[gpr_no*32 +  5], mem[gpr_no*32 +  4],
150
                  mem[gpr_no*32 +  3], mem[gpr_no*32 +  2],
151
                  mem[gpr_no*32 +  1], mem[gpr_no*32 +  0] };
152
 
153
   endfunction // get_gpr
154
 
155 481 julius
   // Function to access GPRs (for use by Verilator). No need to hide this one
156
   // from the simulator, since it has an input (as required by IEEE 1364-2001).
157
   function [31:0] set_gpr;
158
      // verilator public
159
      input [aw-1:0]             gpr_no;
160
      input [dw-1:0]             value;
161
 
162
      mem[gpr_no*32 + 31]   = value[31];
163
      mem[gpr_no*32 + 30] = value[30];
164
      mem[gpr_no*32 + 29]  = value[29];
165
      mem[gpr_no*32 + 28] = value[28];
166
      mem[gpr_no*32 + 27]  = value[27];
167
      mem[gpr_no*32 + 26] = value[26];
168
      mem[gpr_no*32 + 25]  = value[25];
169
      mem[gpr_no*32 + 24] = value[24];
170
      mem[gpr_no*32 + 23]  = value[23];
171
      mem[gpr_no*32 + 22] = value[22];
172
      mem[gpr_no*32 + 21]  = value[21];
173
      mem[gpr_no*32 + 20] = value[20];
174
      mem[gpr_no*32 + 19]  = value[19];
175
      mem[gpr_no*32 + 18] = value[18];
176
      mem[gpr_no*32 + 17]  = value[17];
177
      mem[gpr_no*32 + 16] = value[16];
178
      mem[gpr_no*32 + 15]  = value[15];
179
      mem[gpr_no*32 + 14] = value[14];
180
      mem[gpr_no*32 + 13]  = value[13];
181
      mem[gpr_no*32 + 12] = value[12];
182
      mem[gpr_no*32 + 11]  = value[11];
183
      mem[gpr_no*32 + 10] = value[10];
184
      mem[gpr_no*32 +  9]  = value[ 9];
185
      mem[gpr_no*32 +  8] = value[ 8];
186
      mem[gpr_no*32 +  7]  = value[ 7];
187
      mem[gpr_no*32 +  6] = value[ 6];
188
      mem[gpr_no*32 +  5]  = value[ 5];
189
      mem[gpr_no*32 +  4] = value[ 4];
190
      mem[gpr_no*32 +  3]  = value[ 3];
191
      mem[gpr_no*32 +  2] = value[ 2];
192
      mem[gpr_no*32 +  1]  = value[ 1];
193
      mem[gpr_no*32 +  0] = value[ 0];
194
 
195
      set_gpr = 0;
196
 
197
   endfunction // set_gpr
198
`endif //  `ifdef verilator
199
 
200 10 unneback
//
201
// Write port
202
//
203 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
204
        if (rst == `OR1200_RST_VALUE) begin
205 258 julius
                mem <=  {512'h0, 512'h0};
206 10 unneback
        end
207
        else if (ce_w & we_w)
208
                case (addr_w)   // synopsys parallel_case
209 258 julius
                        5'd01: mem[32*1+31:32*1] <=  di_w;
210
                        5'd02: mem[32*2+31:32*2] <=  di_w;
211
                        5'd03: mem[32*3+31:32*3] <=  di_w;
212
                        5'd04: mem[32*4+31:32*4] <=  di_w;
213
                        5'd05: mem[32*5+31:32*5] <=  di_w;
214
                        5'd06: mem[32*6+31:32*6] <=  di_w;
215
                        5'd07: mem[32*7+31:32*7] <=  di_w;
216
                        5'd08: mem[32*8+31:32*8] <=  di_w;
217
                        5'd09: mem[32*9+31:32*9] <=  di_w;
218
                        5'd10: mem[32*10+31:32*10] <=  di_w;
219
                        5'd11: mem[32*11+31:32*11] <=  di_w;
220
                        5'd12: mem[32*12+31:32*12] <=  di_w;
221
                        5'd13: mem[32*13+31:32*13] <=  di_w;
222
                        5'd14: mem[32*14+31:32*14] <=  di_w;
223
                        5'd15: mem[32*15+31:32*15] <=  di_w;
224 141 marcus.erl
`ifdef OR1200_RFRAM_16REG
225
`else
226 258 julius
                        5'd16: mem[32*16+31:32*16] <=  di_w;
227
                        5'd17: mem[32*17+31:32*17] <=  di_w;
228
                        5'd18: mem[32*18+31:32*18] <=  di_w;
229
                        5'd19: mem[32*19+31:32*19] <=  di_w;
230
                        5'd20: mem[32*20+31:32*20] <=  di_w;
231
                        5'd21: mem[32*21+31:32*21] <=  di_w;
232
                        5'd22: mem[32*22+31:32*22] <=  di_w;
233
                        5'd23: mem[32*23+31:32*23] <=  di_w;
234
                        5'd24: mem[32*24+31:32*24] <=  di_w;
235
                        5'd25: mem[32*25+31:32*25] <=  di_w;
236
                        5'd26: mem[32*26+31:32*26] <=  di_w;
237
                        5'd27: mem[32*27+31:32*27] <=  di_w;
238
                        5'd28: mem[32*28+31:32*28] <=  di_w;
239
                        5'd29: mem[32*29+31:32*29] <=  di_w;
240
                        5'd30: mem[32*30+31:32*30] <=  di_w;
241
                        5'd31: mem[32*31+31:32*31] <=  di_w;
242 141 marcus.erl
`endif
243 258 julius
                        default: mem[32*0+31:32*0] <=  32'h0000_0000;
244 10 unneback
                endcase
245
 
246
//
247
// Read port A
248
//
249 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
250
        if (rst == `OR1200_RST_VALUE) begin
251 258 julius
                intaddr_a <=  5'h00;
252 10 unneback
        end
253
        else if (ce_a)
254 258 julius
                intaddr_a <=  addr_a;
255 10 unneback
 
256
always @(mem or intaddr_a)
257
        case (intaddr_a)        // synopsys parallel_case
258
                5'd01: do_a = mem[32*1+31:32*1];
259
                5'd02: do_a = mem[32*2+31:32*2];
260
                5'd03: do_a = mem[32*3+31:32*3];
261
                5'd04: do_a = mem[32*4+31:32*4];
262
                5'd05: do_a = mem[32*5+31:32*5];
263
                5'd06: do_a = mem[32*6+31:32*6];
264
                5'd07: do_a = mem[32*7+31:32*7];
265
                5'd08: do_a = mem[32*8+31:32*8];
266
                5'd09: do_a = mem[32*9+31:32*9];
267
                5'd10: do_a = mem[32*10+31:32*10];
268
                5'd11: do_a = mem[32*11+31:32*11];
269
                5'd12: do_a = mem[32*12+31:32*12];
270
                5'd13: do_a = mem[32*13+31:32*13];
271
                5'd14: do_a = mem[32*14+31:32*14];
272
                5'd15: do_a = mem[32*15+31:32*15];
273 141 marcus.erl
`ifdef OR1200_RFRAM_16REG
274
`else
275 10 unneback
                5'd16: do_a = mem[32*16+31:32*16];
276
                5'd17: do_a = mem[32*17+31:32*17];
277
                5'd18: do_a = mem[32*18+31:32*18];
278
                5'd19: do_a = mem[32*19+31:32*19];
279
                5'd20: do_a = mem[32*20+31:32*20];
280
                5'd21: do_a = mem[32*21+31:32*21];
281
                5'd22: do_a = mem[32*22+31:32*22];
282
                5'd23: do_a = mem[32*23+31:32*23];
283
                5'd24: do_a = mem[32*24+31:32*24];
284
                5'd25: do_a = mem[32*25+31:32*25];
285
                5'd26: do_a = mem[32*26+31:32*26];
286
                5'd27: do_a = mem[32*27+31:32*27];
287
                5'd28: do_a = mem[32*28+31:32*28];
288
                5'd29: do_a = mem[32*29+31:32*29];
289
                5'd30: do_a = mem[32*30+31:32*30];
290 141 marcus.erl
                5'd31: do_a = mem[32*31+31:32*31];
291
`endif
292
                default: do_a = 32'h0000_0000;
293 10 unneback
        endcase
294
 
295
//
296
// Read port B
297
//
298 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
299
        if (rst == `OR1200_RST_VALUE) begin
300 258 julius
                intaddr_b <=  5'h00;
301 10 unneback
        end
302
        else if (ce_b)
303 258 julius
                intaddr_b <=  addr_b;
304 10 unneback
 
305
always @(mem or intaddr_b)
306
        case (intaddr_b)        // synopsys parallel_case
307
                5'd01: do_b = mem[32*1+31:32*1];
308
                5'd02: do_b = mem[32*2+31:32*2];
309
                5'd03: do_b = mem[32*3+31:32*3];
310
                5'd04: do_b = mem[32*4+31:32*4];
311
                5'd05: do_b = mem[32*5+31:32*5];
312
                5'd06: do_b = mem[32*6+31:32*6];
313
                5'd07: do_b = mem[32*7+31:32*7];
314
                5'd08: do_b = mem[32*8+31:32*8];
315
                5'd09: do_b = mem[32*9+31:32*9];
316
                5'd10: do_b = mem[32*10+31:32*10];
317
                5'd11: do_b = mem[32*11+31:32*11];
318
                5'd12: do_b = mem[32*12+31:32*12];
319
                5'd13: do_b = mem[32*13+31:32*13];
320
                5'd14: do_b = mem[32*14+31:32*14];
321
                5'd15: do_b = mem[32*15+31:32*15];
322 141 marcus.erl
`ifdef OR1200_RFRAM_16REG
323
`else
324 10 unneback
                5'd16: do_b = mem[32*16+31:32*16];
325
                5'd17: do_b = mem[32*17+31:32*17];
326
                5'd18: do_b = mem[32*18+31:32*18];
327
                5'd19: do_b = mem[32*19+31:32*19];
328
                5'd20: do_b = mem[32*20+31:32*20];
329
                5'd21: do_b = mem[32*21+31:32*21];
330
                5'd22: do_b = mem[32*22+31:32*22];
331
                5'd23: do_b = mem[32*23+31:32*23];
332
                5'd24: do_b = mem[32*24+31:32*24];
333
                5'd25: do_b = mem[32*25+31:32*25];
334
                5'd26: do_b = mem[32*26+31:32*26];
335
                5'd27: do_b = mem[32*27+31:32*27];
336
                5'd28: do_b = mem[32*28+31:32*28];
337
                5'd29: do_b = mem[32*29+31:32*29];
338
                5'd30: do_b = mem[32*30+31:32*30];
339 141 marcus.erl
                5'd31: do_b = mem[32*31+31:32*31];
340
`endif
341
                default: do_b = 32'h0000_0000;
342 10 unneback
        endcase
343
 
344
endmodule

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