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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's register file generic memory                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Generic (flip-flop based) register file memory              ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing                                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_rfram_generic.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Defines added, coding style changed. 
//
// Revision 1.3  2004/06/08 18:16:32  lampret
// GPR0 hardwired to zero.
//
// Revision 1.2  2002/09/03 22:28:21  lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.1  2002/06/08 16:23:30  lampret
// Generic flip-flop based memory macro for register file.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_rfram_generic(
        // Clock and reset
        clk, rst,
 
        // Port A
        ce_a, addr_a, do_a,
 
        // Port B
        ce_b, addr_b, do_b,
 
        // Port W
        ce_w, we_w, addr_w, di_w
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Port A
//
input                           ce_a;
input   [aw-1:0]         addr_a;
output  [dw-1:0]         do_a;
 
//
// Port B
//
input                           ce_b;
input   [aw-1:0]         addr_b;
output  [dw-1:0]         do_b;
 
//
// Port W
//
input                           ce_w;
input                           we_w;
input   [aw-1:0]         addr_w;
input   [dw-1:0]         di_w;
 
//
// Internal wires and regs
//
reg     [aw-1:0]         intaddr_a;
reg     [aw-1:0]         intaddr_b;
`ifdef OR1200_RFRAM_16REG
reg     [16*dw-1:0]              mem;
`else
reg     [32*dw-1:0]              mem;
`endif
reg     [dw-1:0]         do_a;
reg     [dw-1:0]         do_b;
 
`ifdef verilator
   // Function to access GPRs (for use by Verilator). No need to hide this one
   // from the simulator, since it has an input (as required by IEEE 1364-2001).
   function [31:0] get_gpr;
      // verilator public
      input [aw-1:0]             gpr_no;
 
      get_gpr = { mem[gpr_no*32 + 31], mem[gpr_no*32 + 30],
                  mem[gpr_no*32 + 29], mem[gpr_no*32 + 28],
                  mem[gpr_no*32 + 27], mem[gpr_no*32 + 26],
                  mem[gpr_no*32 + 25], mem[gpr_no*32 + 24],
                  mem[gpr_no*32 + 23], mem[gpr_no*32 + 22],
                  mem[gpr_no*32 + 21], mem[gpr_no*32 + 20],
                  mem[gpr_no*32 + 19], mem[gpr_no*32 + 18],
                  mem[gpr_no*32 + 17], mem[gpr_no*32 + 16],
                  mem[gpr_no*32 + 15], mem[gpr_no*32 + 14],
                  mem[gpr_no*32 + 13], mem[gpr_no*32 + 12],
                  mem[gpr_no*32 + 11], mem[gpr_no*32 + 10],
                  mem[gpr_no*32 +  9], mem[gpr_no*32 +  8],
                  mem[gpr_no*32 +  7], mem[gpr_no*32 +  6],
                  mem[gpr_no*32 +  5], mem[gpr_no*32 +  4],
                  mem[gpr_no*32 +  3], mem[gpr_no*32 +  2],
                  mem[gpr_no*32 +  1], mem[gpr_no*32 +  0] };
 
   endfunction // get_gpr
 
   // Function to access GPRs (for use by Verilator). No need to hide this one
   // from the simulator, since it has an input (as required by IEEE 1364-2001).
   function [31:0] set_gpr;
      // verilator public
      input [aw-1:0]             gpr_no;
      input [dw-1:0]             value;
 
      mem[gpr_no*32 + 31]   = value[31];
      mem[gpr_no*32 + 30] = value[30];
      mem[gpr_no*32 + 29]  = value[29];
      mem[gpr_no*32 + 28] = value[28];
      mem[gpr_no*32 + 27]  = value[27];
      mem[gpr_no*32 + 26] = value[26];
      mem[gpr_no*32 + 25]  = value[25];
      mem[gpr_no*32 + 24] = value[24];
      mem[gpr_no*32 + 23]  = value[23];
      mem[gpr_no*32 + 22] = value[22];
      mem[gpr_no*32 + 21]  = value[21];
      mem[gpr_no*32 + 20] = value[20];
      mem[gpr_no*32 + 19]  = value[19];
      mem[gpr_no*32 + 18] = value[18];
      mem[gpr_no*32 + 17]  = value[17];
      mem[gpr_no*32 + 16] = value[16];
      mem[gpr_no*32 + 15]  = value[15];
      mem[gpr_no*32 + 14] = value[14];
      mem[gpr_no*32 + 13]  = value[13];
      mem[gpr_no*32 + 12] = value[12];
      mem[gpr_no*32 + 11]  = value[11];
      mem[gpr_no*32 + 10] = value[10];
      mem[gpr_no*32 +  9]  = value[ 9];
      mem[gpr_no*32 +  8] = value[ 8];
      mem[gpr_no*32 +  7]  = value[ 7];
      mem[gpr_no*32 +  6] = value[ 6];
      mem[gpr_no*32 +  5]  = value[ 5];
      mem[gpr_no*32 +  4] = value[ 4];
      mem[gpr_no*32 +  3]  = value[ 3];
      mem[gpr_no*32 +  2] = value[ 2];
      mem[gpr_no*32 +  1]  = value[ 1];
      mem[gpr_no*32 +  0] = value[ 0];
 
      set_gpr = 0;
 
   endfunction // set_gpr
`endif //  `ifdef verilator
 
//
// Write port
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE) begin
                mem <=  {512'h0, 512'h0};
        end
        else if (ce_w & we_w)
                case (addr_w)   // synopsys parallel_case
                        5'd01: mem[32*1+31:32*1] <=  di_w;
                        5'd02: mem[32*2+31:32*2] <=  di_w;
                        5'd03: mem[32*3+31:32*3] <=  di_w;
                        5'd04: mem[32*4+31:32*4] <=  di_w;
                        5'd05: mem[32*5+31:32*5] <=  di_w;
                        5'd06: mem[32*6+31:32*6] <=  di_w;
                        5'd07: mem[32*7+31:32*7] <=  di_w;
                        5'd08: mem[32*8+31:32*8] <=  di_w;
                        5'd09: mem[32*9+31:32*9] <=  di_w;
                        5'd10: mem[32*10+31:32*10] <=  di_w;
                        5'd11: mem[32*11+31:32*11] <=  di_w;
                        5'd12: mem[32*12+31:32*12] <=  di_w;
                        5'd13: mem[32*13+31:32*13] <=  di_w;
                        5'd14: mem[32*14+31:32*14] <=  di_w;
                        5'd15: mem[32*15+31:32*15] <=  di_w;
`ifdef OR1200_RFRAM_16REG
`else
                        5'd16: mem[32*16+31:32*16] <=  di_w;
                        5'd17: mem[32*17+31:32*17] <=  di_w;
                        5'd18: mem[32*18+31:32*18] <=  di_w;
                        5'd19: mem[32*19+31:32*19] <=  di_w;
                        5'd20: mem[32*20+31:32*20] <=  di_w;
                        5'd21: mem[32*21+31:32*21] <=  di_w;
                        5'd22: mem[32*22+31:32*22] <=  di_w;
                        5'd23: mem[32*23+31:32*23] <=  di_w;
                        5'd24: mem[32*24+31:32*24] <=  di_w;
                        5'd25: mem[32*25+31:32*25] <=  di_w;
                        5'd26: mem[32*26+31:32*26] <=  di_w;
                        5'd27: mem[32*27+31:32*27] <=  di_w;
                        5'd28: mem[32*28+31:32*28] <=  di_w;
                        5'd29: mem[32*29+31:32*29] <=  di_w;
                        5'd30: mem[32*30+31:32*30] <=  di_w;
                        5'd31: mem[32*31+31:32*31] <=  di_w;
`endif
                        default: mem[32*0+31:32*0] <=  32'h0000_0000;
                endcase
 
//
// Read port A
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE) begin
                intaddr_a <=  5'h00;
        end
        else if (ce_a)
                intaddr_a <=  addr_a;
 
always @(mem or intaddr_a)
        case (intaddr_a)        // synopsys parallel_case
                5'd01: do_a = mem[32*1+31:32*1];
                5'd02: do_a = mem[32*2+31:32*2];
                5'd03: do_a = mem[32*3+31:32*3];
                5'd04: do_a = mem[32*4+31:32*4];
                5'd05: do_a = mem[32*5+31:32*5];
                5'd06: do_a = mem[32*6+31:32*6];
                5'd07: do_a = mem[32*7+31:32*7];
                5'd08: do_a = mem[32*8+31:32*8];
                5'd09: do_a = mem[32*9+31:32*9];
                5'd10: do_a = mem[32*10+31:32*10];
                5'd11: do_a = mem[32*11+31:32*11];
                5'd12: do_a = mem[32*12+31:32*12];
                5'd13: do_a = mem[32*13+31:32*13];
                5'd14: do_a = mem[32*14+31:32*14];
                5'd15: do_a = mem[32*15+31:32*15];
`ifdef OR1200_RFRAM_16REG
`else
                5'd16: do_a = mem[32*16+31:32*16];
                5'd17: do_a = mem[32*17+31:32*17];
                5'd18: do_a = mem[32*18+31:32*18];
                5'd19: do_a = mem[32*19+31:32*19];
                5'd20: do_a = mem[32*20+31:32*20];
                5'd21: do_a = mem[32*21+31:32*21];
                5'd22: do_a = mem[32*22+31:32*22];
                5'd23: do_a = mem[32*23+31:32*23];
                5'd24: do_a = mem[32*24+31:32*24];
                5'd25: do_a = mem[32*25+31:32*25];
                5'd26: do_a = mem[32*26+31:32*26];
                5'd27: do_a = mem[32*27+31:32*27];
                5'd28: do_a = mem[32*28+31:32*28];
                5'd29: do_a = mem[32*29+31:32*29];
                5'd30: do_a = mem[32*30+31:32*30];
                5'd31: do_a = mem[32*31+31:32*31];
`endif
                default: do_a = 32'h0000_0000;
        endcase
 
//
// Read port B
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE) begin
                intaddr_b <=  5'h00;
        end
        else if (ce_b)
                intaddr_b <=  addr_b;
 
always @(mem or intaddr_b)
        case (intaddr_b)        // synopsys parallel_case
                5'd01: do_b = mem[32*1+31:32*1];
                5'd02: do_b = mem[32*2+31:32*2];
                5'd03: do_b = mem[32*3+31:32*3];
                5'd04: do_b = mem[32*4+31:32*4];
                5'd05: do_b = mem[32*5+31:32*5];
                5'd06: do_b = mem[32*6+31:32*6];
                5'd07: do_b = mem[32*7+31:32*7];
                5'd08: do_b = mem[32*8+31:32*8];
                5'd09: do_b = mem[32*9+31:32*9];
                5'd10: do_b = mem[32*10+31:32*10];
                5'd11: do_b = mem[32*11+31:32*11];
                5'd12: do_b = mem[32*12+31:32*12];
                5'd13: do_b = mem[32*13+31:32*13];
                5'd14: do_b = mem[32*14+31:32*14];
                5'd15: do_b = mem[32*15+31:32*15];
`ifdef OR1200_RFRAM_16REG
`else
                5'd16: do_b = mem[32*16+31:32*16];
                5'd17: do_b = mem[32*17+31:32*17];
                5'd18: do_b = mem[32*18+31:32*18];
                5'd19: do_b = mem[32*19+31:32*19];
                5'd20: do_b = mem[32*20+31:32*20];
                5'd21: do_b = mem[32*21+31:32*21];
                5'd22: do_b = mem[32*22+31:32*22];
                5'd23: do_b = mem[32*23+31:32*23];
                5'd24: do_b = mem[32*24+31:32*24];
                5'd25: do_b = mem[32*25+31:32*25];
                5'd26: do_b = mem[32*26+31:32*26];
                5'd27: do_b = mem[32*27+31:32*27];
                5'd28: do_b = mem[32*28+31:32*28];
                5'd29: do_b = mem[32*29+31:32*29];
                5'd30: do_b = mem[32*30+31:32*30];
                5'd31: do_b = mem[32*31+31:32*31];
`endif
                default: do_b = 32'h0000_0000;
        endcase
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's register file generic memory ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Generic (flip-flop based) register file memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45	141	marcus.erl	`//`
46			`// $Log: or1200_rfram_generic.v,v $`
47			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
48			`// Minor update:`
49			`// Defines added, coding style changed.`
50			`//`
51			`// Revision 1.3 2004/06/08 18:16:32 lampret`
52			`// GPR0 hardwired to zero.`
53			`//`
54	10	unneback	`// Revision 1.2 2002/09/03 22:28:21 lampret`
55			`// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.`
56			`//`
57			`// Revision 1.1 2002/06/08 16:23:30 lampret`
58			`// Generic flip-flop based memory macro for register file.`
59			`//`
60			`//`
61
62			`// synopsys translate_off`
63			`include "timescale.v"
64			`// synopsys translate_on`
65			`include "or1200_defines.v"
66
67			`module or1200_rfram_generic(`
68			`// Clock and reset`
69			`clk, rst,`
70
71			`// Port A`
72			`ce_a, addr_a, do_a,`
73
74			`// Port B`
75			`ce_b, addr_b, do_b,`
76
77			`// Port W`
78			`ce_w, we_w, addr_w, di_w`
79			`);`
80
81			parameter dw = `OR1200_OPERAND_WIDTH;
82			parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
83
84			`//`
85			`// I/O`
86			`//`
87
88			`//`
89			`// Clock and reset`
90			`//`
91			`input clk;`
92			`input rst;`
93
94			`//`
95			`// Port A`
96			`//`
97			`input ce_a;`
98			`input [aw-1:0] addr_a;`
99			`output [dw-1:0] do_a;`
100
101			`//`
102			`// Port B`
103			`//`
104			`input ce_b;`
105			`input [aw-1:0] addr_b;`
106			`output [dw-1:0] do_b;`
107
108			`//`
109			`// Port W`
110			`//`
111			`input ce_w;`
112			`input we_w;`
113			`input [aw-1:0] addr_w;`
114			`input [dw-1:0] di_w;`
115
116			`//`
117			`// Internal wires and regs`
118			`//`
119			`reg [aw-1:0] intaddr_a;`
120			`reg [aw-1:0] intaddr_b;`
121	141	marcus.erl	`ifdef OR1200_RFRAM_16REG
122			`reg [16*dw-1:0] mem;`
123			`else
124	10	unneback	`reg [32*dw-1:0] mem;`
125	141	marcus.erl	`endif
126	10	unneback	`reg [dw-1:0] do_a;`
127			`reg [dw-1:0] do_b;`
128
129	481	julius	`ifdef verilator
130	141	marcus.erl	`// Function to access GPRs (for use by Verilator). No need to hide this one`
131			`// from the simulator, since it has an input (as required by IEEE 1364-2001).`
132			`function [31:0] get_gpr;`
133			`// verilator public`
134			`input [aw-1:0] gpr_no;`
135
136			`get_gpr = { mem[gpr_no32 + 31], mem[gpr_no32 + 30],`
137			`mem[gpr_no32 + 29], mem[gpr_no32 + 28],`
138			`mem[gpr_no32 + 27], mem[gpr_no32 + 26],`
139			`mem[gpr_no32 + 25], mem[gpr_no32 + 24],`
140			`mem[gpr_no32 + 23], mem[gpr_no32 + 22],`
141			`mem[gpr_no32 + 21], mem[gpr_no32 + 20],`
142			`mem[gpr_no32 + 19], mem[gpr_no32 + 18],`
143			`mem[gpr_no32 + 17], mem[gpr_no32 + 16],`
144			`mem[gpr_no32 + 15], mem[gpr_no32 + 14],`
145			`mem[gpr_no32 + 13], mem[gpr_no32 + 12],`
146			`mem[gpr_no32 + 11], mem[gpr_no32 + 10],`
147			`mem[gpr_no32 + 9], mem[gpr_no32 + 8],`
148			`mem[gpr_no32 + 7], mem[gpr_no32 + 6],`
149			`mem[gpr_no32 + 5], mem[gpr_no32 + 4],`
150			`mem[gpr_no32 + 3], mem[gpr_no32 + 2],`
151			`mem[gpr_no32 + 1], mem[gpr_no32 + 0] };`
152
153			`endfunction // get_gpr`
154
155	481	julius	`// Function to access GPRs (for use by Verilator). No need to hide this one`
156			`// from the simulator, since it has an input (as required by IEEE 1364-2001).`
157			`function [31:0] set_gpr;`
158			`// verilator public`
159			`input [aw-1:0] gpr_no;`
160			`input [dw-1:0] value;`
161
162			`mem[gpr_no*32 + 31] = value[31];`
163			`mem[gpr_no*32 + 30] = value[30];`
164			`mem[gpr_no*32 + 29] = value[29];`
165			`mem[gpr_no*32 + 28] = value[28];`
166			`mem[gpr_no*32 + 27] = value[27];`
167			`mem[gpr_no*32 + 26] = value[26];`
168			`mem[gpr_no*32 + 25] = value[25];`
169			`mem[gpr_no*32 + 24] = value[24];`
170			`mem[gpr_no*32 + 23] = value[23];`
171			`mem[gpr_no*32 + 22] = value[22];`
172			`mem[gpr_no*32 + 21] = value[21];`
173			`mem[gpr_no*32 + 20] = value[20];`
174			`mem[gpr_no*32 + 19] = value[19];`
175			`mem[gpr_no*32 + 18] = value[18];`
176			`mem[gpr_no*32 + 17] = value[17];`
177			`mem[gpr_no*32 + 16] = value[16];`
178			`mem[gpr_no*32 + 15] = value[15];`
179			`mem[gpr_no*32 + 14] = value[14];`
180			`mem[gpr_no*32 + 13] = value[13];`
181			`mem[gpr_no*32 + 12] = value[12];`
182			`mem[gpr_no*32 + 11] = value[11];`
183			`mem[gpr_no*32 + 10] = value[10];`
184			`mem[gpr_no*32 + 9] = value[ 9];`
185			`mem[gpr_no*32 + 8] = value[ 8];`
186			`mem[gpr_no*32 + 7] = value[ 7];`
187			`mem[gpr_no*32 + 6] = value[ 6];`
188			`mem[gpr_no*32 + 5] = value[ 5];`
189			`mem[gpr_no*32 + 4] = value[ 4];`
190			`mem[gpr_no*32 + 3] = value[ 3];`
191			`mem[gpr_no*32 + 2] = value[ 2];`
192			`mem[gpr_no*32 + 1] = value[ 1];`
193			`mem[gpr_no*32 + 0] = value[ 0];`
194
195			`set_gpr = 0;`
196
197			`endfunction // set_gpr`
198			`endif // `ifdef verilator
199
200	10	unneback	`//`
201			`// Write port`
202			`//`
203	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
204			if (rst == `OR1200_RST_VALUE) begin
205	258	julius	`mem <= {512'h0, 512'h0};`
206	10	unneback	`end`
207			`else if (ce_w & we_w)`
208			`case (addr_w) // synopsys parallel_case`
209	258	julius	`5'd01: mem[321+31:321] <= di_w;`
210			`5'd02: mem[322+31:322] <= di_w;`
211			`5'd03: mem[323+31:323] <= di_w;`
212			`5'd04: mem[324+31:324] <= di_w;`
213			`5'd05: mem[325+31:325] <= di_w;`
214			`5'd06: mem[326+31:326] <= di_w;`
215			`5'd07: mem[327+31:327] <= di_w;`
216			`5'd08: mem[328+31:328] <= di_w;`
217			`5'd09: mem[329+31:329] <= di_w;`
218			`5'd10: mem[3210+31:3210] <= di_w;`
219			`5'd11: mem[3211+31:3211] <= di_w;`
220			`5'd12: mem[3212+31:3212] <= di_w;`
221			`5'd13: mem[3213+31:3213] <= di_w;`
222			`5'd14: mem[3214+31:3214] <= di_w;`
223			`5'd15: mem[3215+31:3215] <= di_w;`
224	141	marcus.erl	`ifdef OR1200_RFRAM_16REG
225			`else
226	258	julius	`5'd16: mem[3216+31:3216] <= di_w;`
227			`5'd17: mem[3217+31:3217] <= di_w;`
228			`5'd18: mem[3218+31:3218] <= di_w;`
229			`5'd19: mem[3219+31:3219] <= di_w;`
230			`5'd20: mem[3220+31:3220] <= di_w;`
231			`5'd21: mem[3221+31:3221] <= di_w;`
232			`5'd22: mem[3222+31:3222] <= di_w;`
233			`5'd23: mem[3223+31:3223] <= di_w;`
234			`5'd24: mem[3224+31:3224] <= di_w;`
235			`5'd25: mem[3225+31:3225] <= di_w;`
236			`5'd26: mem[3226+31:3226] <= di_w;`
237			`5'd27: mem[3227+31:3227] <= di_w;`
238			`5'd28: mem[3228+31:3228] <= di_w;`
239			`5'd29: mem[3229+31:3229] <= di_w;`
240			`5'd30: mem[3230+31:3230] <= di_w;`
241			`5'd31: mem[3231+31:3231] <= di_w;`
242	141	marcus.erl	`endif
243	258	julius	`default: mem[320+31:320] <= 32'h0000_0000;`
244	10	unneback	`endcase`
245
246			`//`
247			`// Read port A`
248			`//`
249	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
250			if (rst == `OR1200_RST_VALUE) begin
251	258	julius	`intaddr_a <= 5'h00;`
252	10	unneback	`end`
253			`else if (ce_a)`
254	258	julius	`intaddr_a <= addr_a;`
255	10	unneback
256			`always @(mem or intaddr_a)`
257			`case (intaddr_a) // synopsys parallel_case`
258			`5'd01: do_a = mem[321+31:321];`
259			`5'd02: do_a = mem[322+31:322];`
260			`5'd03: do_a = mem[323+31:323];`
261			`5'd04: do_a = mem[324+31:324];`
262			`5'd05: do_a = mem[325+31:325];`
263			`5'd06: do_a = mem[326+31:326];`
264			`5'd07: do_a = mem[327+31:327];`
265			`5'd08: do_a = mem[328+31:328];`
266			`5'd09: do_a = mem[329+31:329];`
267			`5'd10: do_a = mem[3210+31:3210];`
268			`5'd11: do_a = mem[3211+31:3211];`
269			`5'd12: do_a = mem[3212+31:3212];`
270			`5'd13: do_a = mem[3213+31:3213];`
271			`5'd14: do_a = mem[3214+31:3214];`
272			`5'd15: do_a = mem[3215+31:3215];`
273	141	marcus.erl	`ifdef OR1200_RFRAM_16REG
274			`else
275	10	unneback	`5'd16: do_a = mem[3216+31:3216];`
276			`5'd17: do_a = mem[3217+31:3217];`
277			`5'd18: do_a = mem[3218+31:3218];`
278			`5'd19: do_a = mem[3219+31:3219];`
279			`5'd20: do_a = mem[3220+31:3220];`
280			`5'd21: do_a = mem[3221+31:3221];`
281			`5'd22: do_a = mem[3222+31:3222];`
282			`5'd23: do_a = mem[3223+31:3223];`
283			`5'd24: do_a = mem[3224+31:3224];`
284			`5'd25: do_a = mem[3225+31:3225];`
285			`5'd26: do_a = mem[3226+31:3226];`
286			`5'd27: do_a = mem[3227+31:3227];`
287			`5'd28: do_a = mem[3228+31:3228];`
288			`5'd29: do_a = mem[3229+31:3229];`
289			`5'd30: do_a = mem[3230+31:3230];`
290	141	marcus.erl	`5'd31: do_a = mem[3231+31:3231];`
291			`endif
292			`default: do_a = 32'h0000_0000;`
293	10	unneback	`endcase`
294
295			`//`
296			`// Read port B`
297			`//`
298	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
299			if (rst == `OR1200_RST_VALUE) begin
300	258	julius	`intaddr_b <= 5'h00;`
301	10	unneback	`end`
302			`else if (ce_b)`
303	258	julius	`intaddr_b <= addr_b;`
304	10	unneback
305			`always @(mem or intaddr_b)`
306			`case (intaddr_b) // synopsys parallel_case`
307			`5'd01: do_b = mem[321+31:321];`
308			`5'd02: do_b = mem[322+31:322];`
309			`5'd03: do_b = mem[323+31:323];`
310			`5'd04: do_b = mem[324+31:324];`
311			`5'd05: do_b = mem[325+31:325];`
312			`5'd06: do_b = mem[326+31:326];`
313			`5'd07: do_b = mem[327+31:327];`
314			`5'd08: do_b = mem[328+31:328];`
315			`5'd09: do_b = mem[329+31:329];`
316			`5'd10: do_b = mem[3210+31:3210];`
317			`5'd11: do_b = mem[3211+31:3211];`
318			`5'd12: do_b = mem[3212+31:3212];`
319			`5'd13: do_b = mem[3213+31:3213];`
320			`5'd14: do_b = mem[3214+31:3214];`
321			`5'd15: do_b = mem[3215+31:3215];`
322	141	marcus.erl	`ifdef OR1200_RFRAM_16REG
323			`else
324	10	unneback	`5'd16: do_b = mem[3216+31:3216];`
325			`5'd17: do_b = mem[3217+31:3217];`
326			`5'd18: do_b = mem[3218+31:3218];`
327			`5'd19: do_b = mem[3219+31:3219];`
328			`5'd20: do_b = mem[3220+31:3220];`
329			`5'd21: do_b = mem[3221+31:3221];`
330			`5'd22: do_b = mem[3222+31:3222];`
331			`5'd23: do_b = mem[3223+31:3223];`
332			`5'd24: do_b = mem[3224+31:3224];`
333			`5'd25: do_b = mem[3225+31:3225];`
334			`5'd26: do_b = mem[3226+31:3226];`
335			`5'd27: do_b = mem[3227+31:3227];`
336			`5'd28: do_b = mem[3228+31:3228];`
337			`5'd29: do_b = mem[3229+31:3229];`
338			`5'd30: do_b = mem[3230+31:3230];`
339	141	marcus.erl	`5'd31: do_b = mem[3231+31:3231];`
340			`endif
341			`default: do_b = 32'h0000_0000;`
342	10	unneback	`endcase`
343
344			`endmodule`

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