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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sb_fifo.v] - Blame information for rev 142

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Store Buffer FIFO                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Implementation of store buffer FIFO.                        ////
////                                                              ////
////  To Do:                                                      ////
////   - N/A                                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_sb_fifo.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// No update 
//
// Revision 1.3  2002/11/06 13:53:41  simons
// SB mem width fixed.
//
// Revision 1.2  2002/08/22 02:18:55  lampret
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
//
// Revision 1.1  2002/08/18 19:53:08  lampret
// Added store buffer.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_sb_fifo(
        clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o
);
 
parameter dw = 68;
parameter fw = `OR1200_SB_LOG;
parameter fl = `OR1200_SB_ENTRIES;
 
//
// FIFO signals
//
input                   clk_i;  // Clock
input                   rst_i;  // Reset
input   [dw-1:0] dat_i;  // Input data bus
input                   wr_i;   // Write request
input                   rd_i;   // Read request
output [dw-1:0]  dat_o;  // Output data bus
output                  full_o; // FIFO full
output                  empty_o;// FIFO empty
 
//
// Internal regs
//
reg     [dw-1:0] mem [fl-1:0];
reg     [dw-1:0] dat_o;
reg     [fw+1:0] cntr;
reg     [fw-1:0] wr_pntr;
reg     [fw-1:0] rd_pntr;
reg                     empty_o;
reg                     full_o;
 
always @(posedge clk_i or posedge rst_i)
        if (rst_i) begin
                full_o <= #1 1'b0;
                empty_o <= #1 1'b1;
                wr_pntr <= #1 {fw{1'b0}};
                rd_pntr <= #1 {fw{1'b0}};
                cntr <= #1 {fw+2{1'b0}};
                dat_o <= #1 {dw{1'b0}};
        end
        else if (wr_i && rd_i) begin            // FIFO Read and Write
                mem[wr_pntr] <= #1 dat_i;
                if (wr_pntr >= fl-1)
                        wr_pntr <= #1 {fw{1'b0}};
                else
                        wr_pntr <= #1 wr_pntr + 1'b1;
                if (empty_o) begin
                        dat_o <= #1 dat_i;
                end
                else begin
                        dat_o <= #1 mem[rd_pntr];
                end
                if (rd_pntr >= fl-1)
                        rd_pntr <= #1 {fw{1'b0}};
                else
                        rd_pntr <= #1 rd_pntr + 1'b1;
        end
        else if (wr_i && !full_o) begin         // FIFO Write
                mem[wr_pntr] <= #1 dat_i;
                cntr <= #1 cntr + 1'b1;
                empty_o <= #1 1'b0;
                if (cntr >= (fl-1)) begin
                        full_o <= #1 1'b1;
                        cntr <= #1 fl;
                end
                if (wr_pntr >= fl-1)
                        wr_pntr <= #1 {fw{1'b0}};
                else
                        wr_pntr <= #1 wr_pntr + 1'b1;
        end
        else if (rd_i && !empty_o) begin        // FIFO Read
                dat_o <= #1 mem[rd_pntr];
                cntr <= #1 cntr - 1'b1;
                full_o <= #1 1'b0;
                if (cntr <= 1) begin
                        empty_o <= #1 1'b1;
                        cntr <= #1 {fw+2{1'b0}};
                end
                if (rd_pntr >= fl-1)
                        rd_pntr <= #1 {fw{1'b0}};
                else
                        rd_pntr <= #1 rd_pntr + 1'b1;
        end
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Store Buffer FIFO ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implementation of store buffer FIFO. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - N/A ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2002 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	141	marcus.erl	`// $Log: or1200_sb_fifo.v,v $`
47			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
48			`// No update`
49			`//`
50			`// Revision 1.3 2002/11/06 13:53:41 simons`
51			`// SB mem width fixed.`
52			`//`
53	10	unneback	`// Revision 1.2 2002/08/22 02:18:55 lampret`
54			`// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.`
55			`//`
56			`// Revision 1.1 2002/08/18 19:53:08 lampret`
57			`// Added store buffer.`
58			`//`
59			`//`
60
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "or1200_defines.v"
65
66			`module or1200_sb_fifo(`
67			`clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o`
68			`);`
69
70			`parameter dw = 68;`
71			parameter fw = `OR1200_SB_LOG;
72			parameter fl = `OR1200_SB_ENTRIES;
73
74			`//`
75			`// FIFO signals`
76			`//`
77			`input clk_i; // Clock`
78			`input rst_i; // Reset`
79			`input [dw-1:0] dat_i; // Input data bus`
80			`input wr_i; // Write request`
81			`input rd_i; // Read request`
82			`output [dw-1:0] dat_o; // Output data bus`
83			`output full_o; // FIFO full`
84			`output empty_o;// FIFO empty`
85
86			`//`
87			`// Internal regs`
88			`//`
89			`reg [dw-1:0] mem [fl-1:0];`
90			`reg [dw-1:0] dat_o;`
91			`reg [fw+1:0] cntr;`
92			`reg [fw-1:0] wr_pntr;`
93			`reg [fw-1:0] rd_pntr;`
94			`reg empty_o;`
95			`reg full_o;`
96
97			`always @(posedge clk_i or posedge rst_i)`
98			`if (rst_i) begin`
99			`full_o <= #1 1'b0;`
100			`empty_o <= #1 1'b1;`
101			`wr_pntr <= #1 {fw{1'b0}};`
102			`rd_pntr <= #1 {fw{1'b0}};`
103			`cntr <= #1 {fw+2{1'b0}};`
104			`dat_o <= #1 {dw{1'b0}};`
105			`end`
106			`else if (wr_i && rd_i) begin // FIFO Read and Write`
107			`mem[wr_pntr] <= #1 dat_i;`
108			`if (wr_pntr >= fl-1)`
109			`wr_pntr <= #1 {fw{1'b0}};`
110			`else`
111			`wr_pntr <= #1 wr_pntr + 1'b1;`
112			`if (empty_o) begin`
113			`dat_o <= #1 dat_i;`
114			`end`
115			`else begin`
116			`dat_o <= #1 mem[rd_pntr];`
117			`end`
118			`if (rd_pntr >= fl-1)`
119			`rd_pntr <= #1 {fw{1'b0}};`
120			`else`
121			`rd_pntr <= #1 rd_pntr + 1'b1;`
122			`end`
123			`else if (wr_i && !full_o) begin // FIFO Write`
124			`mem[wr_pntr] <= #1 dat_i;`
125			`cntr <= #1 cntr + 1'b1;`
126			`empty_o <= #1 1'b0;`
127			`if (cntr >= (fl-1)) begin`
128			`full_o <= #1 1'b1;`
129			`cntr <= #1 fl;`
130			`end`
131			`if (wr_pntr >= fl-1)`
132			`wr_pntr <= #1 {fw{1'b0}};`
133			`else`
134			`wr_pntr <= #1 wr_pntr + 1'b1;`
135			`end`
136			`else if (rd_i && !empty_o) begin // FIFO Read`
137			`dat_o <= #1 mem[rd_pntr];`
138			`cntr <= #1 cntr - 1'b1;`
139			`full_o <= #1 1'b0;`
140			`if (cntr <= 1) begin`
141			`empty_o <= #1 1'b1;`
142			`cntr <= #1 {fw+2{1'b0}};`
143			`end`
144			`if (rd_pntr >= fl-1)`
145			`rd_pntr <= #1 {fw{1'b0}};`
146			`else`
147			`rd_pntr <= #1 rd_pntr + 1'b1;`
148			`end`
149
150			`endmodule`

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sb_fifo.v] - Blame information for rev 142