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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.2  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
//
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_1024x32(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 10;
parameter dw = 32;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_1024x32 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_1024x32_bist artisan_ssp(
`else
art_hssp_1024x32 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_1024x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x32_bist vs_ssp(
`else
vs_hdsp_1024x32 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[3:0])
);
 
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:4]),
        .EN(ce),
        .WE(we),
        .DO(doq[7:4])
);
 
//
// Block 2
//
RAMB4_S4 ramb4_s4_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:8]),
        .EN(ce),
        .WE(we),
        .DO(doq[11:8])
);
 
//
// Block 3
//
RAMB4_S4 ramb4_s4_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:12]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:12])
);
 
//
// Block 4
//
RAMB4_S4 ramb4_s4_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:16]),
        .EN(ce),
        .WE(we),
        .DO(doq[19:16])
);
 
//
// Block 5
//
RAMB4_S4 ramb4_s4_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:20]),
        .EN(ce),
        .WE(we),
        .DO(doq[23:20])
);
 
//
// Block 6
//
RAMB4_S4 ramb4_s4_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:24]),
        .EN(ce),
        .WE(we),
        .DO(doq[27:24])
);
 
//
// Block 7
//
RAMB4_S4 ramb4_s4_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:28]),
        .EN(ce),
        .WE(we),
        .DO(doq[31:28])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
//
// Block 0
//
RAMB16_S9 ramb16_s9_0(
        .CLK(clk),
        .SSR(rst),
        .ADDR({1'b0,addr}),
        .DI(di[7:0]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we),
        .DO(doq[7:0]),
        .DOP()
);
 
//
// Block 1
//
RAMB16_S9 ramb16_s9_1(
        .CLK(clk),
        .SSR(rst),
        .ADDR({1'b0,addr}),
        .DI(di[15:8]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we),
        .DO(doq[15:8]),
        .DOP()
);
 
//
// Block 2
//
RAMB16_S9 ramb16_s9_2(
        .CLK(clk),
        .SSR(rst),
        .ADDR({1'b0,addr}),
        .DI(di[23:16]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we),
        .DO(doq[23:16]),
        .DOP()
);
 
//
// Block 3
//
RAMB16_S9 ramb16_s9_3(
        .CLK(clk),
        .SSR(rst),
        .ADDR({1'b0,addr}),
        .DI(di[31:24]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we),
        .DO(doq[31:24]),
        .DOP()
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(doq)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x32.v] - Blame information for rev 36

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// - Altera LPM ////`
28			`//// ////`
29			`//// To Do: ////`
30			`//// - xilinx rams need external tri-state logic ////`
31			`//// - fix avant! two-port ram ////`
32			`//// - add additional RAMs ////`
33			`//// ////`
34			`//// Author(s): ////`
35			`//// - Damjan Lampret, lampret@opencores.org ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
40			`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.opencores.org/lgpl.shtml ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// CVS Revision History`
65			`//`
66			`// $Log: not supported by cvs2svn $`
67			`// Revision 1.8 2004/06/08 18:15:32 lampret`
68			`// Changed behavior of the simulation generic models`
69			`//`
70			`// Revision 1.7 2004/04/05 08:29:57 lampret`
71			`// Merged branch_qmem into main tree.`
72			`//`
73			`// Revision 1.3.4.2 2003/12/09 11:46:48 simons`
74			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
75			`//`
76			`// Revision 1.3.4.1 2003/07/08 15:36:37 lampret`
77			`// Added embedded memory QMEM.`
78			`//`
79			`// Revision 1.3 2003/04/07 01:19:07 lampret`
80			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
81			`//`
82			`// Revision 1.2 2002/10/17 20:04:40 lampret`
83			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
84			`//`
85			`// Revision 1.1 2002/01/03 08:16:15 lampret`
86			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
87			`//`
88			`// Revision 1.8 2001/11/02 18:57:14 lampret`
89			`// Modified virtual silicon instantiations.`
90			`//`
91			`// Revision 1.7 2001/10/21 17:57:16 lampret`
92			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
93			`//`
94			`// Revision 1.6 2001/10/14 13:12:09 lampret`
95			`// MP3 version.`
96			`//`
97			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
98			`// no message`
99			`//`
100			`// Revision 1.1 2001/08/09 13:39:33 lampret`
101			`// Major clean-up.`
102			`//`
103			`// Revision 1.2 2001/07/30 05:38:02 lampret`
104			`// Adding empty directories required by HDL coding guidelines`
105			`//`
106			`//`
107
108			`// synopsys translate_off`
109			`include "timescale.v"
110			`// synopsys translate_on`
111			`include "or1200_defines.v"
112
113			`module or1200_spram_1024x32(`
114			`ifdef OR1200_BIST
115			`// RAM BIST`
116			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
117			`endif
118			`// Generic synchronous single-port RAM interface`
119			`clk, rst, ce, we, oe, addr, di, doq`
120			`);`
121
122			`//`
123			`// Default address and data buses width`
124			`//`
125			`parameter aw = 10;`
126			`parameter dw = 32;`
127
128			`ifdef OR1200_BIST
129			`//`
130			`// RAM BIST`
131			`//`
132			`input mbist_si_i;`
133			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
134			`output mbist_so_o;`
135			`endif
136
137			`//`
138			`// Generic synchronous single-port RAM interface`
139			`//`
140			`input clk; // Clock`
141			`input rst; // Reset`
142			`input ce; // Chip enable input`
143			`input we; // Write enable input`
144			`input oe; // Output enable input`
145			`input [aw-1:0] addr; // address bus inputs`
146			`input [dw-1:0] di; // input data bus`
147			`output [dw-1:0] doq; // output data bus`
148
149			`//`
150			`// Internal wires and registers`
151			`//`
152
153			`ifdef OR1200_ARTISAN_SSP
154			`else
155			`ifdef OR1200_VIRTUALSILICON_SSP
156			`else
157			`ifdef OR1200_BIST
158			`assign mbist_so_o = mbist_si_i;`
159			`endif
160			`endif
161			`endif
162
163			`ifdef OR1200_ARTISAN_SSP
164
165			`//`
166			`// Instantiation of ASIC memory:`
167			`//`
168			`// Artisan Synchronous Single-Port RAM (ra1sh)`
169			`//`
170			`ifdef UNUSED
171			`art_hssp_1024x32 #(dw, 1<<aw, aw) artisan_ssp(`
172			`else
173			`ifdef OR1200_BIST
174			`art_hssp_1024x32_bist artisan_ssp(`
175			`else
176			`art_hssp_1024x32 artisan_ssp(`
177			`endif
178			`endif
179			`ifdef OR1200_BIST
180			`// RAM BIST`
181			`.mbist_si_i(mbist_si_i),`
182			`.mbist_so_o(mbist_so_o),`
183			`.mbist_ctrl_i(mbist_ctrl_i),`
184			`endif
185			`.CLK(clk),`
186			`.CEN(~ce),`
187			`.WEN(~we),`
188			`.A(addr),`
189			`.D(di),`
190			`.OEN(~oe),`
191			`.Q(doq)`
192			`);`
193
194			`else
195
196			`ifdef OR1200_AVANT_ATP
197
198			`//`
199			`// Instantiation of ASIC memory:`
200			`//`
201			`// Avant! Asynchronous Two-Port RAM`
202			`//`
203			`avant_atp avant_atp(`
204			`.web(~we),`
205			`.reb(),`
206			`.oeb(~oe),`
207			`.rcsb(),`
208			`.wcsb(),`
209			`.ra(addr),`
210			`.wa(addr),`
211			`.di(di),`
212			`.doq(doq)`
213			`);`
214
215			`else
216
217			`ifdef OR1200_VIRAGE_SSP
218
219			`//`
220			`// Instantiation of ASIC memory:`
221			`//`
222			`// Virage Synchronous 1-port R/W RAM`
223			`//`
224			`virage_ssp virage_ssp(`
225			`.clk(clk),`
226			`.adr(addr),`
227			`.d(di),`
228			`.we(we),`
229			`.oe(oe),`
230			`.me(ce),`
231			`.q(doq)`
232			`);`
233
234			`else
235
236			`ifdef OR1200_VIRTUALSILICON_SSP
237
238			`//`
239			`// Instantiation of ASIC memory:`
240			`//`
241			`// Virtual Silicon Single-Port Synchronous SRAM`
242			`//`
243			`ifdef UNUSED
244			`vs_hdsp_1024x32 #(1<<aw, aw-1, dw-1) vs_ssp(`
245			`else
246			`ifdef OR1200_BIST
247			`vs_hdsp_1024x32_bist vs_ssp(`
248			`else
249			`vs_hdsp_1024x32 vs_ssp(`
250			`endif
251			`endif
252			`ifdef OR1200_BIST
253			`// RAM BIST`
254			`.mbist_si_i(mbist_si_i),`
255			`.mbist_so_o(mbist_so_o),`
256			`.mbist_ctrl_i(mbist_ctrl_i),`
257			`endif
258			`.CK(clk),`
259			`.ADR(addr),`
260			`.DI(di),`
261			`.WEN(~we),`
262			`.CEN(~ce),`
263			`.OEN(~oe),`
264			`.DOUT(doq)`
265			`);`
266
267			`else
268
269			`ifdef OR1200_XILINX_RAMB4
270
271			`//`
272			`// Instantiation of FPGA memory:`
273			`//`
274			`// Virtex/Spartan2`
275			`//`
276
277			`//`
278			`// Block 0`
279			`//`
280			`RAMB4_S4 ramb4_s4_0(`
281			`.CLK(clk),`
282			`.RST(rst),`
283			`.ADDR(addr),`
284			`.DI(di[3:0]),`
285			`.EN(ce),`
286			`.WE(we),`
287			`.DO(doq[3:0])`
288			`);`
289
290			`//`
291			`// Block 1`
292			`//`
293			`RAMB4_S4 ramb4_s4_1(`
294			`.CLK(clk),`
295			`.RST(rst),`
296			`.ADDR(addr),`
297			`.DI(di[7:4]),`
298			`.EN(ce),`
299			`.WE(we),`
300			`.DO(doq[7:4])`
301			`);`
302
303			`//`
304			`// Block 2`
305			`//`
306			`RAMB4_S4 ramb4_s4_2(`
307			`.CLK(clk),`
308			`.RST(rst),`
309			`.ADDR(addr),`
310			`.DI(di[11:8]),`
311			`.EN(ce),`
312			`.WE(we),`
313			`.DO(doq[11:8])`
314			`);`
315
316			`//`
317			`// Block 3`
318			`//`
319			`RAMB4_S4 ramb4_s4_3(`
320			`.CLK(clk),`
321			`.RST(rst),`
322			`.ADDR(addr),`
323			`.DI(di[15:12]),`
324			`.EN(ce),`
325			`.WE(we),`
326			`.DO(doq[15:12])`
327			`);`
328
329			`//`
330			`// Block 4`
331			`//`
332			`RAMB4_S4 ramb4_s4_4(`
333			`.CLK(clk),`
334			`.RST(rst),`
335			`.ADDR(addr),`
336			`.DI(di[19:16]),`
337			`.EN(ce),`
338			`.WE(we),`
339			`.DO(doq[19:16])`
340			`);`
341
342			`//`
343			`// Block 5`
344			`//`
345			`RAMB4_S4 ramb4_s4_5(`
346			`.CLK(clk),`
347			`.RST(rst),`
348			`.ADDR(addr),`
349			`.DI(di[23:20]),`
350			`.EN(ce),`
351			`.WE(we),`
352			`.DO(doq[23:20])`
353			`);`
354
355			`//`
356			`// Block 6`
357			`//`
358			`RAMB4_S4 ramb4_s4_6(`
359			`.CLK(clk),`
360			`.RST(rst),`
361			`.ADDR(addr),`
362			`.DI(di[27:24]),`
363			`.EN(ce),`
364			`.WE(we),`
365			`.DO(doq[27:24])`
366			`);`
367
368			`//`
369			`// Block 7`
370			`//`
371			`RAMB4_S4 ramb4_s4_7(`
372			`.CLK(clk),`
373			`.RST(rst),`
374			`.ADDR(addr),`
375			`.DI(di[31:28]),`
376			`.EN(ce),`
377			`.WE(we),`
378			`.DO(doq[31:28])`
379			`);`
380
381			`else
382
383			`ifdef OR1200_XILINX_RAMB16
384
385			`//`
386			`// Instantiation of FPGA memory:`
387			`//`
388			`// Virtex4/Spartan3E`
389			`//`
390			`// Added By Nir Mor`
391			`//`
392
393			`//`
394			`// Block 0`
395			`//`
396			`RAMB16_S9 ramb16_s9_0(`
397			`.CLK(clk),`
398			`.SSR(rst),`
399			`.ADDR({1'b0,addr}),`
400			`.DI(di[7:0]),`
401			`.DIP(1'b0),`
402			`.EN(ce),`
403			`.WE(we),`
404			`.DO(doq[7:0]),`
405			`.DOP()`
406			`);`
407
408			`//`
409			`// Block 1`
410			`//`
411			`RAMB16_S9 ramb16_s9_1(`
412			`.CLK(clk),`
413			`.SSR(rst),`
414			`.ADDR({1'b0,addr}),`
415			`.DI(di[15:8]),`
416			`.DIP(1'b0),`
417			`.EN(ce),`
418			`.WE(we),`
419			`.DO(doq[15:8]),`
420			`.DOP()`
421			`);`
422
423			`//`
424			`// Block 2`
425			`//`
426			`RAMB16_S9 ramb16_s9_2(`
427			`.CLK(clk),`
428			`.SSR(rst),`
429			`.ADDR({1'b0,addr}),`
430			`.DI(di[23:16]),`
431			`.DIP(1'b0),`
432			`.EN(ce),`
433			`.WE(we),`
434			`.DO(doq[23:16]),`
435			`.DOP()`
436			`);`
437
438			`//`
439			`// Block 3`
440			`//`
441			`RAMB16_S9 ramb16_s9_3(`
442			`.CLK(clk),`
443			`.SSR(rst),`
444			`.ADDR({1'b0,addr}),`
445			`.DI(di[31:24]),`
446			`.DIP(1'b0),`
447			`.EN(ce),`
448			`.WE(we),`
449			`.DO(doq[31:24]),`
450			`.DOP()`
451			`);`
452
453			`else
454
455			`ifdef OR1200_ALTERA_LPM
456
457			`//`
458			`// Instantiation of FPGA memory:`
459			`//`
460			`// Altera LPM`
461			`//`
462			`// Added By Jamil Khatib`
463			`//`
464
465			`wire wr;`
466
467			`assign wr = ce & we;`
468
469			`initial $display("Using Altera LPM.");`
470
471			`lpm_ram_dq lpm_ram_dq_component (`
472			`.address(addr),`
473			`.inclock(clk),`
474			`.outclock(clk),`
475			`.data(di),`
476			`.we(wr),`
477			`.q(doq)`
478			`);`
479
480			`defparam lpm_ram_dq_component.lpm_width = dw,`
481			`lpm_ram_dq_component.lpm_widthad = aw,`
482			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
483			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
484			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
485			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
486			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
487
488			`else
489
490			`//`
491			`// Generic single-port synchronous RAM model`
492			`//`
493
494			`//`
495			`// Generic RAM's registers and wires`
496			`//`
497			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
498			`reg [aw-1:0] addr_reg; // RAM address register`
499
500			`//`
501			`// Data output drivers`
502			`//`
503			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
504
505			`//`
506			`// RAM address register`
507			`//`
508			`always @(posedge clk or posedge rst)`
509			`if (rst)`
510			`addr_reg <= #1 {aw{1'b0}};`
511			`else if (ce)`
512			`addr_reg <= #1 addr;`
513
514			`//`
515			`// RAM write`
516			`//`
517			`always @(posedge clk)`
518			`if (ce && we)`
519			`mem[addr] <= #1 di;`
520
521			`endif // !OR1200_ALTERA_LPM
522			`endif // !OR1200_XILINX_RAMB16
523			`endif // !OR1200_XILINX_RAMB4
524			`endif // !OR1200_VIRTUALSILICON_SSP
525			`endif // !OR1200_VIRAGE_SSP
526			`endif // !OR1200_AVANT_ATP
527			`endif // !OR1200_ARTISAN_SSP
528
529			`endmodule`