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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM with byte write signals ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.2  2003/10/17 07:59:44  markom
// mbist signals updated according to newest convention
//
// Revision 1.1  2003/08/27 08:38:36  simons
// Added support for rams with byte write access.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_1024x32_bw(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                   mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
output                  mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input   [3:0]           we;     // Write enable input
input                   oe;     // Output enable input
input   [9:0]           addr;   // address bus inputs
input   [31:0]          di;     // input data bus
output  [31:0]          doq;     // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_1024x32_bw artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_1024x32_bw_bist artisan_ssp(
`else
art_hssp_1024x32_bw artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef OR1200_BIST
wire mbist_si_i_ram_0;
wire mbist_si_i_ram_1;
wire mbist_si_i_ram_2;
wire mbist_si_i_ram_3;
wire mbist_so_o_ram_0;
wire mbist_so_o_ram_1;
wire mbist_so_o_ram_2;
wire mbist_so_o_ram_3;
assign mbist_si_i_ram_0 = mbist_si_i;
assign mbist_si_i_ram_1 = mbist_so_o_ram_0;
assign mbist_si_i_ram_2 = mbist_so_o_ram_1;
assign mbist_si_i_ram_3 = mbist_so_o_ram_2;
assign mbist_so_o = mbist_so_o_ram_3;
`endif
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_0(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_0(
`else
vs_hdsp_1024x8 vs_ssp_0(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_0),
        .mbist_so_o(mbist_so_o_ram_0),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[7:0]),
        .WEN(~we[0]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq[7:0])
);
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_1(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_1(
`else
vs_hdsp_1024x8 vs_ssp_1(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_1),
        .mbist_so_o(mbist_so_o_ram_1),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[15:8]),
        .WEN(~we[1]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq[15:8])
);
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_2(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_2(
`else
vs_hdsp_1024x8 vs_ssp_2(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_2),
        .mbist_so_o(mbist_so_o_ram_2),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[23:16]),
        .WEN(~we[2]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq[23:16])
);
 
`ifdef UNUSED
vs_hdsp_1024x8 vs_ssp_3(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp_3(
`else
vs_hdsp_1024x8 vs_ssp_3(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i_ram_3),
        .mbist_so_o(mbist_so_o_ram_3),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di[31:24]),
        .WEN(~we[3]),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq[31:24])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:0]),
        .EN(ce),
        .WE(we[0]),
        .DO(doq[3:0])
);
 
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:4]),
        .EN(ce),
        .WE(we[0]),
        .DO(doq[7:4])
);
 
//
// Block 2
//
RAMB4_S4 ramb4_s4_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[11:8]),
        .EN(ce),
        .WE(we[1]),
        .DO(doq[11:8])
);
 
//
// Block 3
//
RAMB4_S4 ramb4_s4_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:12]),
        .EN(ce),
        .WE(we[1]),
        .DO(doq[15:12])
);
 
//
// Block 4
//
RAMB4_S4 ramb4_s4_4(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[19:16]),
        .EN(ce),
        .WE(we[2]),
        .DO(doq[19:16])
);
 
//
// Block 5
//
RAMB4_S4 ramb4_s4_5(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[23:20]),
        .EN(ce),
        .WE(we[2]),
        .DO(doq[23:20])
);
 
//
// Block 6
//
RAMB4_S4 ramb4_s4_6(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[27:24]),
        .EN(ce),
        .WE(we[3]),
        .DO(doq[27:24])
);
 
//
// Block 7
//
RAMB4_S4 ramb4_s4_7(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[31:28]),
        .EN(ce),
        .WE(we[3]),
        .DO(doq[31:28])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
//
// Block 0
//
RAMB16_S9 ramb16_s9_0(
        .CLK(clk),
        .SSR(rst),
        .ADDR({1'b0,addr}),
        .DI(di[7:0]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we[0]),
        .DO(doq[7:0]),
        .DOP()
);
 
//
// Block 1
//
RAMB16_S9 ramb16_s9_1(
        .CLK(clk),
        .SSR(rst),
        .ADDR({1'b0,addr}),
        .DI(di[15:8]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we[1]),
        .DO(doq[15:8]),
        .DOP()
);
 
//
// Block 2
//
RAMB16_S9 ramb16_s9_2(
        .CLK(clk),
        .SSR(rst),
        .ADDR({1'b0,addr}),
        .DI(di[23:16]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we[2]),
        .DO(doq[23:16]),
        .DOP()
);
 
//
// Block 3
//
RAMB16_S9 ramb16_s9_3(
        .CLK(clk),
        .SSR(rst),
        .ADDR({1'b0,addr}),
        .DI(di[31:24]),
        .DIP(1'b0),
        .EN(ce),
        .WE(we[3]),
        .DO(doq[31:24]),
        .DOP()
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [7:0]        mem_0 [1023:0];              // RAM content
reg     [7:0]        mem_1 [1023:0];              // RAM content
reg     [7:0]        mem_2 [1023:0];              // RAM content
reg     [7:0]        mem_3 [1023:0];              // RAM content
reg     [9:0]        addr_reg;                 // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? {mem_3[addr_reg], mem_2[addr_reg], mem_1[addr_reg], mem_0[addr_reg]} : {32{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 10'h000;
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write byte 0
//
always @(posedge clk)
        if (ce && we[0])
                mem_0[addr] <= #1 di[7:0];
 
//
// RAM write byte 1
//
always @(posedge clk)
        if (ce && we[1])
                mem_1[addr] <= #1 di[15:8];
 
//
// RAM write byte 2
//
always @(posedge clk)
        if (ce && we[2])
                mem_2[addr] <= #1 di[23:16];
 
//
// RAM write byte 3
//
always @(posedge clk)
        if (ce && we[3])
                mem_3[addr] <= #1 di[31:24];
 
 
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x32_bw.v] - Blame information for rev 39

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM with byte write signals ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31			`//// - add additional RAMs ////`
32			`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66			`// Revision 1.3 2004/06/08 18:15:32 lampret`
67			`// Changed behavior of the simulation generic models`
68			`//`
69			`// Revision 1.2 2003/10/17 07:59:44 markom`
70			`// mbist signals updated according to newest convention`
71			`//`
72			`// Revision 1.1 2003/08/27 08:38:36 simons`
73			`// Added support for rams with byte write access.`
74			`//`
75			`//`
76
77			`// synopsys translate_off`
78			`include "timescale.v"
79			`// synopsys translate_on`
80			`include "or1200_defines.v"
81
82			`module or1200_spram_1024x32_bw(`
83			`ifdef OR1200_BIST
84			`// RAM BIST`
85			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
86			`endif
87			`// Generic synchronous single-port RAM interface`
88			`clk, rst, ce, we, oe, addr, di, doq`
89			`);`
90
91			`ifdef OR1200_BIST
92			`//`
93			`// RAM BIST`
94			`//`
95			`input mbist_si_i;`
96			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
97			`output mbist_so_o;`
98			`endif
99
100			`//`
101			`// Generic synchronous single-port RAM interface`
102			`//`
103			`input clk; // Clock`
104			`input rst; // Reset`
105			`input ce; // Chip enable input`
106			`input [3:0] we; // Write enable input`
107			`input oe; // Output enable input`
108			`input [9:0] addr; // address bus inputs`
109			`input [31:0] di; // input data bus`
110			`output [31:0] doq; // output data bus`
111
112			`//`
113			`// Internal wires and registers`
114			`//`
115
116			`ifdef OR1200_ARTISAN_SSP
117			`else
118			`ifdef OR1200_VIRTUALSILICON_SSP
119			`else
120			`ifdef OR1200_BIST
121			`assign mbist_so_o = mbist_si_i;`
122			`endif
123			`endif
124			`endif
125
126
127			`ifdef OR1200_ARTISAN_SSP
128
129			`//`
130			`// Instantiation of ASIC memory:`
131			`//`
132			`// Artisan Synchronous Single-Port RAM (ra1sh)`
133			`//`
134			`ifdef UNUSED
135			`art_hssp_1024x32_bw artisan_ssp(`
136			`else
137			`ifdef OR1200_BIST
138			`art_hssp_1024x32_bw_bist artisan_ssp(`
139			`else
140			`art_hssp_1024x32_bw artisan_ssp(`
141			`endif
142			`endif
143			`ifdef OR1200_BIST
144			`// RAM BIST`
145			`.mbist_si_i(mbist_si_i),`
146			`.mbist_so_o(mbist_so_o),`
147			`.mbist_ctrl_i(mbist_ctrl_i),`
148			`endif
149			`.CLK(clk),`
150			`.CEN(~ce),`
151			`.WEN(~we),`
152			`.A(addr),`
153			`.D(di),`
154			`.OEN(~oe),`
155			`.Q(doq)`
156			`);`
157
158			`else
159
160			`ifdef OR1200_AVANT_ATP
161
162			`//`
163			`// Instantiation of ASIC memory:`
164			`//`
165			`// Avant! Asynchronous Two-Port RAM`
166			`//`
167			`avant_atp avant_atp(`
168			`.web(~we),`
169			`.reb(),`
170			`.oeb(~oe),`
171			`.rcsb(),`
172			`.wcsb(),`
173			`.ra(addr),`
174			`.wa(addr),`
175			`.di(di),`
176			`.doq(doq)`
177			`);`
178
179			`else
180
181			`ifdef OR1200_VIRAGE_SSP
182
183			`//`
184			`// Instantiation of ASIC memory:`
185			`//`
186			`// Virage Synchronous 1-port R/W RAM`
187			`//`
188			`virage_ssp virage_ssp(`
189			`.clk(clk),`
190			`.adr(addr),`
191			`.d(di),`
192			`.we(we),`
193			`.oe(oe),`
194			`.me(ce),`
195			`.q(doq)`
196			`);`
197
198			`else
199
200			`ifdef OR1200_VIRTUALSILICON_SSP
201
202			`//`
203			`// Instantiation of ASIC memory:`
204			`//`
205			`// Virtual Silicon Single-Port Synchronous SRAM`
206			`//`
207			`ifdef OR1200_BIST
208			`wire mbist_si_i_ram_0;`
209			`wire mbist_si_i_ram_1;`
210			`wire mbist_si_i_ram_2;`
211			`wire mbist_si_i_ram_3;`
212			`wire mbist_so_o_ram_0;`
213			`wire mbist_so_o_ram_1;`
214			`wire mbist_so_o_ram_2;`
215			`wire mbist_so_o_ram_3;`
216			`assign mbist_si_i_ram_0 = mbist_si_i;`
217			`assign mbist_si_i_ram_1 = mbist_so_o_ram_0;`
218			`assign mbist_si_i_ram_2 = mbist_so_o_ram_1;`
219			`assign mbist_si_i_ram_3 = mbist_so_o_ram_2;`
220			`assign mbist_so_o = mbist_so_o_ram_3;`
221			`endif
222
223			`ifdef UNUSED
224			`vs_hdsp_1024x8 vs_ssp_0(`
225			`else
226			`ifdef OR1200_BIST
227			`vs_hdsp_1024x8_bist vs_ssp_0(`
228			`else
229			`vs_hdsp_1024x8 vs_ssp_0(`
230			`endif
231			`endif
232			`ifdef OR1200_BIST
233			`// RAM BIST`
234			`.mbist_si_i(mbist_si_i_ram_0),`
235			`.mbist_so_o(mbist_so_o_ram_0),`
236			`.mbist_ctrl_i(mbist_ctrl_i),`
237			`endif
238			`.CK(clk),`
239			`.ADR(addr),`
240			`.DI(di[7:0]),`
241			`.WEN(~we[0]),`
242			`.CEN(~ce),`
243			`.OEN(~oe),`
244			`.DOUT(doq[7:0])`
245			`);`
246
247			`ifdef UNUSED
248			`vs_hdsp_1024x8 vs_ssp_1(`
249			`else
250			`ifdef OR1200_BIST
251			`vs_hdsp_1024x8_bist vs_ssp_1(`
252			`else
253			`vs_hdsp_1024x8 vs_ssp_1(`
254			`endif
255			`endif
256			`ifdef OR1200_BIST
257			`// RAM BIST`
258			`.mbist_si_i(mbist_si_i_ram_1),`
259			`.mbist_so_o(mbist_so_o_ram_1),`
260			`.mbist_ctrl_i(mbist_ctrl_i),`
261			`endif
262			`.CK(clk),`
263			`.ADR(addr),`
264			`.DI(di[15:8]),`
265			`.WEN(~we[1]),`
266			`.CEN(~ce),`
267			`.OEN(~oe),`
268			`.DOUT(doq[15:8])`
269			`);`
270
271			`ifdef UNUSED
272			`vs_hdsp_1024x8 vs_ssp_2(`
273			`else
274			`ifdef OR1200_BIST
275			`vs_hdsp_1024x8_bist vs_ssp_2(`
276			`else
277			`vs_hdsp_1024x8 vs_ssp_2(`
278			`endif
279			`endif
280			`ifdef OR1200_BIST
281			`// RAM BIST`
282			`.mbist_si_i(mbist_si_i_ram_2),`
283			`.mbist_so_o(mbist_so_o_ram_2),`
284			`.mbist_ctrl_i(mbist_ctrl_i),`
285			`endif
286			`.CK(clk),`
287			`.ADR(addr),`
288			`.DI(di[23:16]),`
289			`.WEN(~we[2]),`
290			`.CEN(~ce),`
291			`.OEN(~oe),`
292			`.DOUT(doq[23:16])`
293			`);`
294
295			`ifdef UNUSED
296			`vs_hdsp_1024x8 vs_ssp_3(`
297			`else
298			`ifdef OR1200_BIST
299			`vs_hdsp_1024x8_bist vs_ssp_3(`
300			`else
301			`vs_hdsp_1024x8 vs_ssp_3(`
302			`endif
303			`endif
304			`ifdef OR1200_BIST
305			`// RAM BIST`
306			`.mbist_si_i(mbist_si_i_ram_3),`
307			`.mbist_so_o(mbist_so_o_ram_3),`
308			`.mbist_ctrl_i(mbist_ctrl_i),`
309			`endif
310			`.CK(clk),`
311			`.ADR(addr),`
312			`.DI(di[31:24]),`
313			`.WEN(~we[3]),`
314			`.CEN(~ce),`
315			`.OEN(~oe),`
316			`.DOUT(doq[31:24])`
317			`);`
318
319			`else
320
321			`ifdef OR1200_XILINX_RAMB4
322
323			`//`
324			`// Instantiation of FPGA memory:`
325			`//`
326			`// Virtex/Spartan2`
327			`//`
328
329			`//`
330			`// Block 0`
331			`//`
332			`RAMB4_S4 ramb4_s4_0(`
333			`.CLK(clk),`
334			`.RST(rst),`
335			`.ADDR(addr),`
336			`.DI(di[3:0]),`
337			`.EN(ce),`
338			`.WE(we[0]),`
339			`.DO(doq[3:0])`
340			`);`
341
342			`//`
343			`// Block 1`
344			`//`
345			`RAMB4_S4 ramb4_s4_1(`
346			`.CLK(clk),`
347			`.RST(rst),`
348			`.ADDR(addr),`
349			`.DI(di[7:4]),`
350			`.EN(ce),`
351			`.WE(we[0]),`
352			`.DO(doq[7:4])`
353			`);`
354
355			`//`
356			`// Block 2`
357			`//`
358			`RAMB4_S4 ramb4_s4_2(`
359			`.CLK(clk),`
360			`.RST(rst),`
361			`.ADDR(addr),`
362			`.DI(di[11:8]),`
363			`.EN(ce),`
364			`.WE(we[1]),`
365			`.DO(doq[11:8])`
366			`);`
367
368			`//`
369			`// Block 3`
370			`//`
371			`RAMB4_S4 ramb4_s4_3(`
372			`.CLK(clk),`
373			`.RST(rst),`
374			`.ADDR(addr),`
375			`.DI(di[15:12]),`
376			`.EN(ce),`
377			`.WE(we[1]),`
378			`.DO(doq[15:12])`
379			`);`
380
381			`//`
382			`// Block 4`
383			`//`
384			`RAMB4_S4 ramb4_s4_4(`
385			`.CLK(clk),`
386			`.RST(rst),`
387			`.ADDR(addr),`
388			`.DI(di[19:16]),`
389			`.EN(ce),`
390			`.WE(we[2]),`
391			`.DO(doq[19:16])`
392			`);`
393
394			`//`
395			`// Block 5`
396			`//`
397			`RAMB4_S4 ramb4_s4_5(`
398			`.CLK(clk),`
399			`.RST(rst),`
400			`.ADDR(addr),`
401			`.DI(di[23:20]),`
402			`.EN(ce),`
403			`.WE(we[2]),`
404			`.DO(doq[23:20])`
405			`);`
406
407			`//`
408			`// Block 6`
409			`//`
410			`RAMB4_S4 ramb4_s4_6(`
411			`.CLK(clk),`
412			`.RST(rst),`
413			`.ADDR(addr),`
414			`.DI(di[27:24]),`
415			`.EN(ce),`
416			`.WE(we[3]),`
417			`.DO(doq[27:24])`
418			`);`
419
420			`//`
421			`// Block 7`
422			`//`
423			`RAMB4_S4 ramb4_s4_7(`
424			`.CLK(clk),`
425			`.RST(rst),`
426			`.ADDR(addr),`
427			`.DI(di[31:28]),`
428			`.EN(ce),`
429			`.WE(we[3]),`
430			`.DO(doq[31:28])`
431			`);`
432
433			`else
434
435			`ifdef OR1200_XILINX_RAMB16
436
437			`//`
438			`// Instantiation of FPGA memory:`
439			`//`
440			`// Virtex4/Spartan3E`
441			`//`
442			`// Added By Nir Mor`
443			`//`
444
445			`//`
446			`// Block 0`
447			`//`
448			`RAMB16_S9 ramb16_s9_0(`
449			`.CLK(clk),`
450			`.SSR(rst),`
451			`.ADDR({1'b0,addr}),`
452			`.DI(di[7:0]),`
453			`.DIP(1'b0),`
454			`.EN(ce),`
455			`.WE(we[0]),`
456			`.DO(doq[7:0]),`
457			`.DOP()`
458			`);`
459
460			`//`
461			`// Block 1`
462			`//`
463			`RAMB16_S9 ramb16_s9_1(`
464			`.CLK(clk),`
465			`.SSR(rst),`
466			`.ADDR({1'b0,addr}),`
467			`.DI(di[15:8]),`
468			`.DIP(1'b0),`
469			`.EN(ce),`
470			`.WE(we[1]),`
471			`.DO(doq[15:8]),`
472			`.DOP()`
473			`);`
474
475			`//`
476			`// Block 2`
477			`//`
478			`RAMB16_S9 ramb16_s9_2(`
479			`.CLK(clk),`
480			`.SSR(rst),`
481			`.ADDR({1'b0,addr}),`
482			`.DI(di[23:16]),`
483			`.DIP(1'b0),`
484			`.EN(ce),`
485			`.WE(we[2]),`
486			`.DO(doq[23:16]),`
487			`.DOP()`
488			`);`
489
490			`//`
491			`// Block 3`
492			`//`
493			`RAMB16_S9 ramb16_s9_3(`
494			`.CLK(clk),`
495			`.SSR(rst),`
496			`.ADDR({1'b0,addr}),`
497			`.DI(di[31:24]),`
498			`.DIP(1'b0),`
499			`.EN(ce),`
500			`.WE(we[3]),`
501			`.DO(doq[31:24]),`
502			`.DOP()`
503			`);`
504
505			`else
506
507			`//`
508			`// Generic single-port synchronous RAM model`
509			`//`
510
511			`//`
512			`// Generic RAM's registers and wires`
513			`//`
514			`reg [7:0] mem_0 [1023:0]; // RAM content`
515			`reg [7:0] mem_1 [1023:0]; // RAM content`
516			`reg [7:0] mem_2 [1023:0]; // RAM content`
517			`reg [7:0] mem_3 [1023:0]; // RAM content`
518			`reg [9:0] addr_reg; // RAM address register`
519
520			`//`
521			`// Data output drivers`
522			`//`
523			`assign doq = (oe) ? {mem_3[addr_reg], mem_2[addr_reg], mem_1[addr_reg], mem_0[addr_reg]} : {32{1'b0}};`
524
525			`//`
526			`// RAM address register`
527			`//`
528			`always @(posedge clk or posedge rst)`
529			`if (rst)`
530			`addr_reg <= #1 10'h000;`
531			`else if (ce)`
532			`addr_reg <= #1 addr;`
533
534			`//`
535			`// RAM write byte 0`
536			`//`
537			`always @(posedge clk)`
538			`if (ce && we[0])`
539			`mem_0[addr] <= #1 di[7:0];`
540
541			`//`
542			`// RAM write byte 1`
543			`//`
544			`always @(posedge clk)`
545			`if (ce && we[1])`
546			`mem_1[addr] <= #1 di[15:8];`
547
548			`//`
549			`// RAM write byte 2`
550			`//`
551			`always @(posedge clk)`
552			`if (ce && we[2])`
553			`mem_2[addr] <= #1 di[23:16];`
554
555			`//`
556			`// RAM write byte 3`
557			`//`
558			`always @(posedge clk)`
559			`if (ce && we[3])`
560			`mem_3[addr] <= #1 di[31:24];`
561
562
563			`endif // !OR1200_XILINX_RAMB16
564			`endif // !OR1200_XILINX_RAMB4
565			`endif // !OR1200_VIRTUALSILICON_SSP
566			`endif // !OR1200_VIRAGE_SSP
567			`endif // !OR1200_AVANT_ATP
568			`endif // !OR1200_ARTISAN_SSP
569
570			`endmodule`