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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x32_bw.v] - Blame information for rev 247

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Generic Single-Port Synchronous RAM with byte write signals ////
4
////                                                              ////
5
////  This file is part of memory library available from          ////
6
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  This block is a wrapper with common single-port             ////
10
////  synchronous memory interface for different                  ////
11
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
12
////  interface it also provides behavioral model of generic      ////
13
////  single-port synchronous RAM.                                ////
14
////  It should be used in all OPENCORES designs that want to be  ////
15
////  portable accross different target technologies and          ////
16
////  independent of target memory.                               ////
17
////                                                              ////
18
////  Supported ASIC RAMs are:                                    ////
19
////  - Artisan Single-Port Sync RAM                              ////
20
////  - Avant! Two-Port Sync RAM (*)                              ////
21
////  - Virage Single-Port Sync RAM                               ////
22
////  - Virtual Silicon Single-Port Sync RAM                      ////
23
////                                                              ////
24
////  Supported FPGA RAMs are:                                    ////
25
////  - Xilinx Virtex RAMB16                                      ////
26
////  - Xilinx Virtex RAMB4                                       ////
27
////                                                              ////
28
////  To Do:                                                      ////
29
////   - xilinx rams need external tri-state logic                ////
30
////   - fix avant! two-port ram                                  ////
31
////   - add additional RAMs                                      ////
32
////                                                              ////
33
////  Author(s):                                                  ////
34
////      - Damjan Lampret, lampret@opencores.org                 ////
35
////                                                              ////
36
//////////////////////////////////////////////////////////////////////
37
////                                                              ////
38
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
39
////                                                              ////
40
//// This source file may be used and distributed without         ////
41
//// restriction provided that this copyright statement is not    ////
42
//// removed from the file and that any derivative work contains  ////
43
//// the original copyright notice and the associated disclaimer. ////
44
////                                                              ////
45
//// This source file is free software; you can redistribute it   ////
46
//// and/or modify it under the terms of the GNU Lesser General   ////
47
//// Public License as published by the Free Software Foundation; ////
48
//// either version 2.1 of the License, or (at your option) any   ////
49
//// later version.                                               ////
50
////                                                              ////
51
//// This source is distributed in the hope that it will be       ////
52
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
53
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
54
//// PURPOSE.  See the GNU Lesser General Public License for more ////
55
//// details.                                                     ////
56
////                                                              ////
57
//// You should have received a copy of the GNU Lesser General    ////
58
//// Public License along with this source; if not, download it   ////
59
//// from http://www.opencores.org/lgpl.shtml                     ////
60
////                                                              ////
61
//////////////////////////////////////////////////////////////////////
62
//
63
// CVS Revision History
64
//
65 142 marcus.erl
// $Log: or1200_spram_1024x32_bw.v,v $
66
// Revision 2.0  2010/06/30 11:00:00  ORSoC
67
// Minor update: 
68
// Coding style changed.
69
//
70
// Revision 1.4  2005/10/19 11:37:56  jcastillo
71
// Added support for RAMB16 Xilinx4/Spartan3 primitives
72
//
73 10 unneback
// Revision 1.3  2004/06/08 18:15:32  lampret
74
// Changed behavior of the simulation generic models
75
//
76
// Revision 1.2  2003/10/17 07:59:44  markom
77
// mbist signals updated according to newest convention
78
//
79
// Revision 1.1  2003/08/27 08:38:36  simons
80
// Added support for rams with byte write access.
81
//
82
//
83
 
84
// synopsys translate_off
85
`include "timescale.v"
86
// synopsys translate_on
87
`include "or1200_defines.v"
88
 
89
module or1200_spram_1024x32_bw(
90
`ifdef OR1200_BIST
91
        // RAM BIST
92
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
93
`endif
94
        // Generic synchronous single-port RAM interface
95
        clk, rst, ce, we, oe, addr, di, doq
96
);
97
 
98
`ifdef OR1200_BIST
99
//
100
// RAM BIST
101
//
102
input                   mbist_si_i;
103
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
104
output                  mbist_so_o;
105
`endif
106
 
107
//
108
// Generic synchronous single-port RAM interface
109
//
110
input                   clk;    // Clock
111
input                   rst;    // Reset
112
input                   ce;     // Chip enable input
113
input   [3:0]           we;     // Write enable input
114
input                   oe;     // Output enable input
115
input   [9:0]           addr;   // address bus inputs
116
input   [31:0]          di;     // input data bus
117
output  [31:0]          doq;     // output data bus
118
 
119
//
120
// Internal wires and registers
121
//
122
 
123
`ifdef OR1200_ARTISAN_SSP
124
`else
125
`ifdef OR1200_VIRTUALSILICON_SSP
126
`else
127
`ifdef OR1200_BIST
128
assign mbist_so_o = mbist_si_i;
129
`endif
130
`endif
131
`endif
132
 
133
 
134
`ifdef OR1200_ARTISAN_SSP
135
 
136
//
137
// Instantiation of ASIC memory:
138
//
139
// Artisan Synchronous Single-Port RAM (ra1sh)
140
//
141
`ifdef UNUSED
142
art_hssp_1024x32_bw artisan_ssp(
143
`else
144
`ifdef OR1200_BIST
145
art_hssp_1024x32_bw_bist artisan_ssp(
146
`else
147
art_hssp_1024x32_bw artisan_ssp(
148
`endif
149
`endif
150
`ifdef OR1200_BIST
151
        // RAM BIST
152
        .mbist_si_i(mbist_si_i),
153
        .mbist_so_o(mbist_so_o),
154
        .mbist_ctrl_i(mbist_ctrl_i),
155
`endif
156
        .CLK(clk),
157
        .CEN(~ce),
158
        .WEN(~we),
159
        .A(addr),
160
        .D(di),
161
        .OEN(~oe),
162
        .Q(doq)
163
);
164
 
165
`else
166
 
167
`ifdef OR1200_AVANT_ATP
168
 
169
//
170
// Instantiation of ASIC memory:
171
//
172
// Avant! Asynchronous Two-Port RAM
173
//
174
avant_atp avant_atp(
175
        .web(~we),
176
        .reb(),
177
        .oeb(~oe),
178
        .rcsb(),
179
        .wcsb(),
180
        .ra(addr),
181
        .wa(addr),
182
        .di(di),
183
        .doq(doq)
184
);
185
 
186
`else
187
 
188
`ifdef OR1200_VIRAGE_SSP
189
 
190
//
191
// Instantiation of ASIC memory:
192
//
193
// Virage Synchronous 1-port R/W RAM
194
//
195
virage_ssp virage_ssp(
196
        .clk(clk),
197
        .adr(addr),
198
        .d(di),
199
        .we(we),
200
        .oe(oe),
201
        .me(ce),
202
        .q(doq)
203
);
204
 
205
`else
206
 
207
`ifdef OR1200_VIRTUALSILICON_SSP
208
 
209
//
210
// Instantiation of ASIC memory:
211
//
212
// Virtual Silicon Single-Port Synchronous SRAM
213
//
214
`ifdef OR1200_BIST
215
wire mbist_si_i_ram_0;
216
wire mbist_si_i_ram_1;
217
wire mbist_si_i_ram_2;
218
wire mbist_si_i_ram_3;
219
wire mbist_so_o_ram_0;
220
wire mbist_so_o_ram_1;
221
wire mbist_so_o_ram_2;
222
wire mbist_so_o_ram_3;
223
assign mbist_si_i_ram_0 = mbist_si_i;
224
assign mbist_si_i_ram_1 = mbist_so_o_ram_0;
225
assign mbist_si_i_ram_2 = mbist_so_o_ram_1;
226
assign mbist_si_i_ram_3 = mbist_so_o_ram_2;
227
assign mbist_so_o = mbist_so_o_ram_3;
228
`endif
229
 
230
`ifdef UNUSED
231
vs_hdsp_1024x8 vs_ssp_0(
232
`else
233
`ifdef OR1200_BIST
234
vs_hdsp_1024x8_bist vs_ssp_0(
235
`else
236
vs_hdsp_1024x8 vs_ssp_0(
237
`endif
238
`endif
239
`ifdef OR1200_BIST
240
        // RAM BIST
241
        .mbist_si_i(mbist_si_i_ram_0),
242
        .mbist_so_o(mbist_so_o_ram_0),
243
        .mbist_ctrl_i(mbist_ctrl_i),
244
`endif
245
        .CK(clk),
246
        .ADR(addr),
247
        .DI(di[7:0]),
248
        .WEN(~we[0]),
249
        .CEN(~ce),
250
        .OEN(~oe),
251
        .DOUT(doq[7:0])
252
);
253
 
254
`ifdef UNUSED
255
vs_hdsp_1024x8 vs_ssp_1(
256
`else
257
`ifdef OR1200_BIST
258
vs_hdsp_1024x8_bist vs_ssp_1(
259
`else
260
vs_hdsp_1024x8 vs_ssp_1(
261
`endif
262
`endif
263
`ifdef OR1200_BIST
264
        // RAM BIST
265
        .mbist_si_i(mbist_si_i_ram_1),
266
        .mbist_so_o(mbist_so_o_ram_1),
267
        .mbist_ctrl_i(mbist_ctrl_i),
268
`endif
269
        .CK(clk),
270
        .ADR(addr),
271
        .DI(di[15:8]),
272
        .WEN(~we[1]),
273
        .CEN(~ce),
274
        .OEN(~oe),
275
        .DOUT(doq[15:8])
276
);
277
 
278
`ifdef UNUSED
279
vs_hdsp_1024x8 vs_ssp_2(
280
`else
281
`ifdef OR1200_BIST
282
vs_hdsp_1024x8_bist vs_ssp_2(
283
`else
284
vs_hdsp_1024x8 vs_ssp_2(
285
`endif
286
`endif
287
`ifdef OR1200_BIST
288
        // RAM BIST
289
        .mbist_si_i(mbist_si_i_ram_2),
290
        .mbist_so_o(mbist_so_o_ram_2),
291
        .mbist_ctrl_i(mbist_ctrl_i),
292
`endif
293
        .CK(clk),
294
        .ADR(addr),
295
        .DI(di[23:16]),
296
        .WEN(~we[2]),
297
        .CEN(~ce),
298
        .OEN(~oe),
299
        .DOUT(doq[23:16])
300
);
301
 
302
`ifdef UNUSED
303
vs_hdsp_1024x8 vs_ssp_3(
304
`else
305
`ifdef OR1200_BIST
306
vs_hdsp_1024x8_bist vs_ssp_3(
307
`else
308
vs_hdsp_1024x8 vs_ssp_3(
309
`endif
310
`endif
311
`ifdef OR1200_BIST
312
        // RAM BIST
313
        .mbist_si_i(mbist_si_i_ram_3),
314
        .mbist_so_o(mbist_so_o_ram_3),
315
        .mbist_ctrl_i(mbist_ctrl_i),
316
`endif
317
        .CK(clk),
318
        .ADR(addr),
319
        .DI(di[31:24]),
320
        .WEN(~we[3]),
321
        .CEN(~ce),
322
        .OEN(~oe),
323
        .DOUT(doq[31:24])
324
);
325
 
326
`else
327
 
328
`ifdef OR1200_XILINX_RAMB4
329
 
330
//
331
// Instantiation of FPGA memory:
332
//
333
// Virtex/Spartan2
334
//
335
 
336
//
337
// Block 0
338
//
339
RAMB4_S4 ramb4_s4_0(
340
        .CLK(clk),
341 142 marcus.erl
        .RST(1'b0),
342 10 unneback
        .ADDR(addr),
343
        .DI(di[3:0]),
344
        .EN(ce),
345
        .WE(we[0]),
346
        .DO(doq[3:0])
347
);
348
 
349
//
350
// Block 1
351
//
352
RAMB4_S4 ramb4_s4_1(
353
        .CLK(clk),
354 142 marcus.erl
        .RST(1'b0),
355 10 unneback
        .ADDR(addr),
356
        .DI(di[7:4]),
357
        .EN(ce),
358
        .WE(we[0]),
359
        .DO(doq[7:4])
360
);
361
 
362
//
363
// Block 2
364
//
365
RAMB4_S4 ramb4_s4_2(
366
        .CLK(clk),
367 142 marcus.erl
        .RST(1'b0),
368 10 unneback
        .ADDR(addr),
369
        .DI(di[11:8]),
370
        .EN(ce),
371
        .WE(we[1]),
372
        .DO(doq[11:8])
373
);
374
 
375
//
376
// Block 3
377
//
378
RAMB4_S4 ramb4_s4_3(
379
        .CLK(clk),
380 142 marcus.erl
        .RST(1'b0),
381 10 unneback
        .ADDR(addr),
382
        .DI(di[15:12]),
383
        .EN(ce),
384
        .WE(we[1]),
385
        .DO(doq[15:12])
386
);
387
 
388
//
389
// Block 4
390
//
391
RAMB4_S4 ramb4_s4_4(
392
        .CLK(clk),
393 142 marcus.erl
        .RST(1'b0),
394 10 unneback
        .ADDR(addr),
395
        .DI(di[19:16]),
396
        .EN(ce),
397
        .WE(we[2]),
398
        .DO(doq[19:16])
399
);
400
 
401
//
402
// Block 5
403
//
404
RAMB4_S4 ramb4_s4_5(
405
        .CLK(clk),
406 142 marcus.erl
        .RST(1'b0),
407 10 unneback
        .ADDR(addr),
408
        .DI(di[23:20]),
409
        .EN(ce),
410
        .WE(we[2]),
411
        .DO(doq[23:20])
412
);
413
 
414
//
415
// Block 6
416
//
417
RAMB4_S4 ramb4_s4_6(
418
        .CLK(clk),
419 142 marcus.erl
        .RST(1'b0),
420 10 unneback
        .ADDR(addr),
421
        .DI(di[27:24]),
422
        .EN(ce),
423
        .WE(we[3]),
424
        .DO(doq[27:24])
425
);
426
 
427
//
428
// Block 7
429
//
430
RAMB4_S4 ramb4_s4_7(
431
        .CLK(clk),
432 142 marcus.erl
        .RST(1'b0),
433 10 unneback
        .ADDR(addr),
434
        .DI(di[31:28]),
435
        .EN(ce),
436
        .WE(we[3]),
437
        .DO(doq[31:28])
438
);
439
 
440
`else
441
 
442
`ifdef OR1200_XILINX_RAMB16
443
 
444
//
445
// Instantiation of FPGA memory:
446
//
447
// Virtex4/Spartan3E
448
//
449
// Added By Nir Mor
450
//
451
 
452
//
453
// Block 0
454
//
455
RAMB16_S9 ramb16_s9_0(
456
        .CLK(clk),
457 142 marcus.erl
        .SSR(1'b0),
458 10 unneback
        .ADDR({1'b0,addr}),
459
        .DI(di[7:0]),
460
        .DIP(1'b0),
461
        .EN(ce),
462
        .WE(we[0]),
463
        .DO(doq[7:0]),
464
        .DOP()
465
);
466
 
467
//
468
// Block 1
469
//
470
RAMB16_S9 ramb16_s9_1(
471
        .CLK(clk),
472 142 marcus.erl
        .SSR(1'b0),
473 10 unneback
        .ADDR({1'b0,addr}),
474
        .DI(di[15:8]),
475
        .DIP(1'b0),
476
        .EN(ce),
477
        .WE(we[1]),
478
        .DO(doq[15:8]),
479
        .DOP()
480
);
481
 
482
//
483
// Block 2
484
//
485
RAMB16_S9 ramb16_s9_2(
486
        .CLK(clk),
487 142 marcus.erl
        .SSR(1'b0),
488 10 unneback
        .ADDR({1'b0,addr}),
489
        .DI(di[23:16]),
490
        .DIP(1'b0),
491
        .EN(ce),
492
        .WE(we[2]),
493
        .DO(doq[23:16]),
494
        .DOP()
495
);
496
 
497
//
498
// Block 3
499
//
500
RAMB16_S9 ramb16_s9_3(
501
        .CLK(clk),
502 142 marcus.erl
        .SSR(1'b0),
503 10 unneback
        .ADDR({1'b0,addr}),
504
        .DI(di[31:24]),
505
        .DIP(1'b0),
506
        .EN(ce),
507
        .WE(we[3]),
508
        .DO(doq[31:24]),
509
        .DOP()
510
);
511
 
512
`else
513
 
514
//
515
// Generic single-port synchronous RAM model
516
//
517
 
518
//
519
// Generic RAM's registers and wires
520
//
521
reg     [7:0]        mem_0 [1023:0];              // RAM content
522
reg     [7:0]        mem_1 [1023:0];              // RAM content
523
reg     [7:0]        mem_2 [1023:0];              // RAM content
524
reg     [7:0]        mem_3 [1023:0];              // RAM content
525
reg     [9:0]        addr_reg;                 // RAM address register
526
 
527
//
528
// Data output drivers
529
//
530
assign doq = (oe) ? {mem_3[addr_reg], mem_2[addr_reg], mem_1[addr_reg], mem_0[addr_reg]} : {32{1'b0}};
531
 
532
//
533
// RAM address register
534
//
535
always @(posedge clk or posedge rst)
536
        if (rst)
537
                addr_reg <= #1 10'h000;
538
        else if (ce)
539
                addr_reg <= #1 addr;
540
 
541
//
542
// RAM write byte 0
543
//
544
always @(posedge clk)
545
        if (ce && we[0])
546
                mem_0[addr] <= #1 di[7:0];
547
 
548
//
549
// RAM write byte 1
550
//
551
always @(posedge clk)
552
        if (ce && we[1])
553
                mem_1[addr] <= #1 di[15:8];
554
 
555
//
556
// RAM write byte 2
557
//
558
always @(posedge clk)
559
        if (ce && we[2])
560
                mem_2[addr] <= #1 di[23:16];
561
 
562
//
563
// RAM write byte 3
564
//
565
always @(posedge clk)
566
        if (ce && we[3])
567
                mem_3[addr] <= #1 di[31:24];
568
 
569
 
570
`endif  // !OR1200_XILINX_RAMB16
571
`endif  // !OR1200_XILINX_RAMB4
572
`endif  // !OR1200_VIRTUALSILICON_SSP
573
`endif  // !OR1200_VIRAGE_SSP
574
`endif  // !OR1200_AVANT_ATP
575
`endif  // !OR1200_ARTISAN_SSP
576
 
577
endmodule

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