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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////                                                              ////
////  To Do:                                                      ////
////   - add support for other RAM's                              ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_128x32.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Coding style changed.
//
// Revision 1.3  2005/10/19 11:37:56  jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.2  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_128x32(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 7;
parameter dw = 32;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
`endif
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
`endif
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(1'b0),
        .ADDR({1'b0, addr}),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(1'b0),
        .ADDR({1'b0, addr}),
        .DI(di[31:16]),
        .EN(ce),
        .WE(we),
        .DO(doq[31:16])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
RAMB16_S36 ramb16_s36(
        .CLK(clk),
        .SSR(1'b0),
        .ADDR({2'b00, addr}),
        .DI(di),
        .DIP(4'h0),
        .EN(ce),
        .WE(we),
        .DO(doq),
        .DOP()
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                addr_reg <=  {aw{1'b0}};
        else if (ce)
                addr_reg <=  addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <=  di;
 
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_128x32.v] - Blame information for rev 443

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// ////`
20			`//// Supported FPGA RAMs are: ////`
21			`//// - Xilinx Virtex RAMB16 ////`
22			`//// - Xilinx Virtex RAMB4 ////`
23			`//// ////`
24			`//// To Do: ////`
25			`//// - add support for other RAM's ////`
26			`//// - xilinx rams need external tri-state logic ////`
27			`//// - fix avant! two-port ram ////`
28			`//// - add additional RAMs ////`
29			`//// ////`
30			`//// Author(s): ////`
31			`//// - Damjan Lampret, lampret@opencores.org ////`
32			`//// ////`
33			`//////////////////////////////////////////////////////////////////////`
34			`//// ////`
35			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
36			`//// ////`
37			`//// This source file may be used and distributed without ////`
38			`//// restriction provided that this copyright statement is not ////`
39			`//// removed from the file and that any derivative work contains ////`
40			`//// the original copyright notice and the associated disclaimer. ////`
41			`//// ////`
42			`//// This source file is free software; you can redistribute it ////`
43			`//// and/or modify it under the terms of the GNU Lesser General ////`
44			`//// Public License as published by the Free Software Foundation; ////`
45			`//// either version 2.1 of the License, or (at your option) any ////`
46			`//// later version. ////`
47			`//// ////`
48			`//// This source is distributed in the hope that it will be ////`
49			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
50			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
51			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
52			`//// details. ////`
53			`//// ////`
54			`//// You should have received a copy of the GNU Lesser General ////`
55			`//// Public License along with this source; if not, download it ////`
56			`//// from http://www.opencores.org/lgpl.shtml ////`
57			`//// ////`
58			`//////////////////////////////////////////////////////////////////////`
59			`//`
60			`// CVS Revision History`
61			`//`
62	142	marcus.erl	`// $Log: or1200_spram_128x32.v,v $`
63			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
64			`// Minor update:`
65			`// Coding style changed.`
66			`//`
67			`// Revision 1.3 2005/10/19 11:37:56 jcastillo`
68			`// Added support for RAMB16 Xilinx4/Spartan3 primitives`
69			`//`
70	10	unneback	`// Revision 1.2 2004/06/08 18:15:32 lampret`
71			`// Changed behavior of the simulation generic models`
72			`//`
73			`// Revision 1.1 2004/04/08 11:00:46 simont`
74			`// Add support for 512B instruction cache.`
75			`//`
76			`//`
77			`//`
78
79			`// synopsys translate_off`
80			`include "timescale.v"
81			`// synopsys translate_on`
82			`include "or1200_defines.v"
83
84			`module or1200_spram_128x32(`
85			`ifdef OR1200_BIST
86			`// RAM BIST`
87			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
88			`endif
89			`// Generic synchronous single-port RAM interface`
90			`clk, rst, ce, we, oe, addr, di, doq`
91			`);`
92
93			`//`
94			`// Default address and data buses width`
95			`//`
96			`parameter aw = 7;`
97			`parameter dw = 32;`
98
99			`ifdef OR1200_BIST
100			`//`
101			`// RAM BIST`
102			`//`
103			`input mbist_si_i;`
104			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
105			`output mbist_so_o;`
106			`endif
107
108			`//`
109			`// Generic synchronous single-port RAM interface`
110			`//`
111			`input clk; // Clock`
112			`input rst; // Reset`
113			`input ce; // Chip enable input`
114			`input we; // Write enable input`
115			`input oe; // Output enable input`
116			`input [aw-1:0] addr; // address bus inputs`
117			`input [dw-1:0] di; // input data bus`
118			`output [dw-1:0] doq; // output data bus`
119
120			`//`
121			`// Internal wires and registers`
122			`//`
123
124			`ifdef OR1200_ARTISAN_SSP
125			`else
126			`ifdef OR1200_VIRTUALSILICON_SSP
127			`else
128			`ifdef OR1200_BIST
129			`endif
130			`endif
131			`endif
132
133			`ifdef OR1200_ARTISAN_SSP
134
135			`//`
136			`// Instantiation of ASIC memory:`
137			`//`
138			`// Artisan Synchronous Single-Port RAM (ra1sh)`
139			`//`
140			`ifdef UNUSED
141			`else
142			`ifdef OR1200_BIST
143			`else
144			`endif
145			`endif
146			`ifdef OR1200_BIST
147			`endif
148			`else
149
150			`ifdef OR1200_AVANT_ATP
151
152			`//`
153			`// Instantiation of ASIC memory:`
154			`//`
155			`// Avant! Asynchronous Two-Port RAM`
156			`//`
157
158			`else
159
160			`ifdef OR1200_VIRAGE_SSP
161
162			`//`
163			`// Instantiation of ASIC memory:`
164			`//`
165			`// Virage Synchronous 1-port R/W RAM`
166			`//`
167
168			`else
169
170			`ifdef OR1200_VIRTUALSILICON_SSP
171
172			`//`
173			`// Instantiation of ASIC memory:`
174			`//`
175			`// Virtual Silicon Single-Port Synchronous SRAM`
176			`//`
177			`ifdef UNUSED
178			`else
179			`ifdef OR1200_BIST
180			`else
181			`endif
182			`endif
183			`ifdef OR1200_BIST
184			`// RAM BIST`
185			`endif
186
187			`else
188
189			`ifdef OR1200_XILINX_RAMB4
190
191			`//`
192			`// Instantiation of FPGA memory:`
193			`//`
194			`// Virtex/Spartan2`
195			`//`
196
197			`//`
198			`// Block 0`
199			`//`
200			`RAMB4_S16 ramb4_s16_0(`
201			`.CLK(clk),`
202	142	marcus.erl	`.RST(1'b0),`
203	10	unneback	`.ADDR({1'b0, addr}),`
204			`.DI(di[15:0]),`
205			`.EN(ce),`
206			`.WE(we),`
207			`.DO(doq[15:0])`
208			`);`
209
210			`//`
211			`// Block 1`
212			`//`
213			`RAMB4_S16 ramb4_s16_1(`
214			`.CLK(clk),`
215	142	marcus.erl	`.RST(1'b0),`
216	10	unneback	`.ADDR({1'b0, addr}),`
217			`.DI(di[31:16]),`
218			`.EN(ce),`
219			`.WE(we),`
220			`.DO(doq[31:16])`
221			`);`
222
223			`else
224
225			`ifdef OR1200_XILINX_RAMB16
226
227			`//`
228			`// Instantiation of FPGA memory:`
229			`//`
230			`// Virtex4/Spartan3E`
231			`//`
232			`// Added By Nir Mor`
233			`//`
234
235			`RAMB16_S36 ramb16_s36(`
236			`.CLK(clk),`
237	142	marcus.erl	`.SSR(1'b0),`
238	10	unneback	`.ADDR({2'b00, addr}),`
239			`.DI(di),`
240			`.DIP(4'h0),`
241			`.EN(ce),`
242			`.WE(we),`
243			`.DO(doq),`
244			`.DOP()`
245			`);`
246
247			`else
248
249			`//`
250			`// Generic single-port synchronous RAM model`
251			`//`
252
253			`//`
254			`// Generic RAM's registers and wires`
255			`//`
256			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
257			`reg [aw-1:0] addr_reg; // RAM address register`
258
259			`//`
260			`// Data output drivers`
261			`//`
262			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
263
264			`//`
265			`// RAM address register`
266			`//`
267	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
268			if (rst == `OR1200_RST_VALUE)
269	258	julius	`addr_reg <= {aw{1'b0}};`
270	10	unneback	`else if (ce)`
271	258	julius	`addr_reg <= addr;`
272	10	unneback
273			`//`
274			`// RAM write`
275			`//`
276			`always @(posedge clk)`
277			`if (ce && we)`
278	258	julius	`mem[addr] <= di;`
279	10	unneback
280			`endif // !OR1200_XILINX_RAMB16
281			`endif // !OR1200_XILINX_RAMB4
282			`endif // !OR1200_VIRTUALSILICON_SSP
283			`endif // !OR1200_VIRAGE_SSP
284			`endif // !OR1200_AVANT_ATP
285			`endif // !OR1200_ARTISAN_SSP
286
287			`endmodule`