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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x8.v] - Blame information for rev 42

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_2048x8(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 8;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x8_bist artisan_ssp(
`else
art_hssp_2048x8 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp(
`else
vs_hdsp_2048x8 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[1:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[1:0])
);
 
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:2]),
        .EN(ce),
        .WE(we),
        .DO(doq[3:2])
);
 
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[5:4]),
        .EN(ce),
        .WE(we),
        .DO(doq[5:4])
);
 
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:6]),
        .EN(ce),
        .WE(we),
        .DO(doq[7:6])
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
RAMB16_S9 ramb16_s9(
        .CLK(clk),
        .SSR(rst),
        .ADDR(addr),
        .DI(di),
        .DIP(1'b0),
        .EN(ce),
        .WE(we),
        .DO(doq),
        .DOP()
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(doq)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x8.v] - Blame information for rev 42

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// - Altera LPM ////`
28			`//// ////`
29			`//// To Do: ////`
30			`//// - xilinx rams need external tri-state logic ////`
31			`//// - fix avant! two-port ram ////`
32			`//// - add additional RAMs ////`
33			`//// ////`
34			`//// Author(s): ////`
35			`//// - Damjan Lampret, lampret@opencores.org ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
40			`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.opencores.org/lgpl.shtml ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// CVS Revision History`
65			`//`
66			`// $Log: not supported by cvs2svn $`
67			`// Revision 1.8 2004/06/08 18:15:32 lampret`
68			`// Changed behavior of the simulation generic models`
69			`//`
70			`// Revision 1.7 2004/04/05 08:29:57 lampret`
71			`// Merged branch_qmem into main tree.`
72			`//`
73			`// Revision 1.3.4.1 2003/12/09 11:46:48 simons`
74			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
75			`//`
76			`// Revision 1.3 2003/04/07 01:19:07 lampret`
77			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
78			`//`
79			`// Revision 1.2 2002/10/17 20:04:40 lampret`
80			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
81			`//`
82			`// Revision 1.1 2002/01/03 08:16:15 lampret`
83			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
84			`//`
85			`// Revision 1.8 2001/11/02 18:57:14 lampret`
86			`// Modified virtual silicon instantiations.`
87			`//`
88			`// Revision 1.7 2001/10/21 17:57:16 lampret`
89			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
90			`//`
91			`// Revision 1.6 2001/10/14 13:12:09 lampret`
92			`// MP3 version.`
93			`//`
94			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
95			`// no message`
96			`//`
97			`// Revision 1.1 2001/08/09 13:39:33 lampret`
98			`// Major clean-up.`
99			`//`
100			`// Revision 1.2 2001/07/30 05:38:02 lampret`
101			`// Adding empty directories required by HDL coding guidelines`
102			`//`
103			`//`
104
105			`// synopsys translate_off`
106			`include "timescale.v"
107			`// synopsys translate_on`
108			`include "or1200_defines.v"
109
110			`module or1200_spram_2048x8(`
111			`ifdef OR1200_BIST
112			`// RAM BIST`
113			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
114			`endif
115			`// Generic synchronous single-port RAM interface`
116			`clk, rst, ce, we, oe, addr, di, doq`
117			`);`
118
119			`//`
120			`// Default address and data buses width`
121			`//`
122			`parameter aw = 11;`
123			`parameter dw = 8;`
124
125			`ifdef OR1200_BIST
126			`//`
127			`// RAM BIST`
128			`//`
129			`input mbist_si_i;`
130			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
131			`output mbist_so_o;`
132			`endif
133
134			`//`
135			`// Generic synchronous single-port RAM interface`
136			`//`
137			`input clk; // Clock`
138			`input rst; // Reset`
139			`input ce; // Chip enable input`
140			`input we; // Write enable input`
141			`input oe; // Output enable input`
142			`input [aw-1:0] addr; // address bus inputs`
143			`input [dw-1:0] di; // input data bus`
144			`output [dw-1:0] doq; // output data bus`
145
146			`//`
147			`// Internal wires and registers`
148			`//`
149
150			`ifdef OR1200_ARTISAN_SSP
151			`else
152			`ifdef OR1200_VIRTUALSILICON_SSP
153			`else
154			`ifdef OR1200_BIST
155			`assign mbist_so_o = mbist_si_i;`
156			`endif
157			`endif
158			`endif
159
160			`ifdef OR1200_ARTISAN_SSP
161
162			`//`
163			`// Instantiation of ASIC memory:`
164			`//`
165			`// Artisan Synchronous Single-Port RAM (ra1sh)`
166			`//`
167			`ifdef UNUSED
168			`art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(`
169			`else
170			`ifdef OR1200_BIST
171			`art_hssp_2048x8_bist artisan_ssp(`
172			`else
173			`art_hssp_2048x8 artisan_ssp(`
174			`endif
175			`endif
176			`ifdef OR1200_BIST
177			`// RAM BIST`
178			`.mbist_si_i(mbist_si_i),`
179			`.mbist_so_o(mbist_so_o),`
180			`.mbist_ctrl_i(mbist_ctrl_i),`
181			`endif
182			`.CLK(clk),`
183			`.CEN(~ce),`
184			`.WEN(~we),`
185			`.A(addr),`
186			`.D(di),`
187			`.OEN(~oe),`
188			`.Q(doq)`
189			`);`
190
191			`else
192
193			`ifdef OR1200_AVANT_ATP
194
195			`//`
196			`// Instantiation of ASIC memory:`
197			`//`
198			`// Avant! Asynchronous Two-Port RAM`
199			`//`
200			`avant_atp avant_atp(`
201			`.web(~we),`
202			`.reb(),`
203			`.oeb(~oe),`
204			`.rcsb(),`
205			`.wcsb(),`
206			`.ra(addr),`
207			`.wa(addr),`
208			`.di(di),`
209			`.doq(doq)`
210			`);`
211
212			`else
213
214			`ifdef OR1200_VIRAGE_SSP
215
216			`//`
217			`// Instantiation of ASIC memory:`
218			`//`
219			`// Virage Synchronous 1-port R/W RAM`
220			`//`
221			`virage_ssp virage_ssp(`
222			`.clk(clk),`
223			`.adr(addr),`
224			`.d(di),`
225			`.we(we),`
226			`.oe(oe),`
227			`.me(ce),`
228			`.q(doq)`
229			`);`
230
231			`else
232
233			`ifdef OR1200_VIRTUALSILICON_SSP
234
235			`//`
236			`// Instantiation of ASIC memory:`
237			`//`
238			`// Virtual Silicon Single-Port Synchronous SRAM`
239			`//`
240			`ifdef UNUSED
241			`vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(`
242			`else
243			`ifdef OR1200_BIST
244			`vs_hdsp_2048x8_bist vs_ssp(`
245			`else
246			`vs_hdsp_2048x8 vs_ssp(`
247			`endif
248			`endif
249			`ifdef OR1200_BIST
250			`// RAM BIST`
251			`.mbist_si_i(mbist_si_i),`
252			`.mbist_so_o(mbist_so_o),`
253			`.mbist_ctrl_i(mbist_ctrl_i),`
254			`endif
255			`.CK(clk),`
256			`.ADR(addr),`
257			`.DI(di),`
258			`.WEN(~we),`
259			`.CEN(~ce),`
260			`.OEN(~oe),`
261			`.DOUT(doq)`
262			`);`
263
264			`else
265
266			`ifdef OR1200_XILINX_RAMB4
267
268			`//`
269			`// Instantiation of FPGA memory:`
270			`//`
271			`// Virtex/Spartan2`
272			`//`
273
274			`//`
275			`// Block 0`
276			`//`
277			`RAMB4_S2 ramb4_s2_0(`
278			`.CLK(clk),`
279			`.RST(rst),`
280			`.ADDR(addr),`
281			`.DI(di[1:0]),`
282			`.EN(ce),`
283			`.WE(we),`
284			`.DO(doq[1:0])`
285			`);`
286
287			`//`
288			`// Block 1`
289			`//`
290			`RAMB4_S2 ramb4_s2_1(`
291			`.CLK(clk),`
292			`.RST(rst),`
293			`.ADDR(addr),`
294			`.DI(di[3:2]),`
295			`.EN(ce),`
296			`.WE(we),`
297			`.DO(doq[3:2])`
298			`);`
299
300			`//`
301			`// Block 2`
302			`//`
303			`RAMB4_S2 ramb4_s2_2(`
304			`.CLK(clk),`
305			`.RST(rst),`
306			`.ADDR(addr),`
307			`.DI(di[5:4]),`
308			`.EN(ce),`
309			`.WE(we),`
310			`.DO(doq[5:4])`
311			`);`
312
313			`//`
314			`// Block 3`
315			`//`
316			`RAMB4_S2 ramb4_s2_3(`
317			`.CLK(clk),`
318			`.RST(rst),`
319			`.ADDR(addr),`
320			`.DI(di[7:6]),`
321			`.EN(ce),`
322			`.WE(we),`
323			`.DO(doq[7:6])`
324			`);`
325
326			`else
327
328			`ifdef OR1200_XILINX_RAMB16
329
330			`//`
331			`// Instantiation of FPGA memory:`
332			`//`
333			`// Virtex4/Spartan3E`
334			`//`
335			`// Added By Nir Mor`
336			`//`
337
338			`RAMB16_S9 ramb16_s9(`
339			`.CLK(clk),`
340			`.SSR(rst),`
341			`.ADDR(addr),`
342			`.DI(di),`
343			`.DIP(1'b0),`
344			`.EN(ce),`
345			`.WE(we),`
346			`.DO(doq),`
347			`.DOP()`
348			`);`
349
350			`else
351
352			`ifdef OR1200_ALTERA_LPM
353
354			`//`
355			`// Instantiation of FPGA memory:`
356			`//`
357			`// Altera LPM`
358			`//`
359			`// Added By Jamil Khatib`
360			`//`
361
362			`wire wr;`
363
364			`assign wr = ce & we;`
365
366			`initial $display("Using Altera LPM.");`
367
368			`lpm_ram_dq lpm_ram_dq_component (`
369			`.address(addr),`
370			`.inclock(clk),`
371			`.outclock(clk),`
372			`.data(di),`
373			`.we(wr),`
374			`.q(doq)`
375			`);`
376
377			`defparam lpm_ram_dq_component.lpm_width = dw,`
378			`lpm_ram_dq_component.lpm_widthad = aw,`
379			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
380			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
381			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
382			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
383			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
384
385			`else
386
387			`//`
388			`// Generic single-port synchronous RAM model`
389			`//`
390
391			`//`
392			`// Generic RAM's registers and wires`
393			`//`
394			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
395			`reg [aw-1:0] addr_reg; // RAM address register`
396
397			`//`
398			`// Data output drivers`
399			`//`
400			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
401
402			`//`
403			`// RAM address register`
404			`//`
405			`always @(posedge clk or posedge rst)`
406			`if (rst)`
407			`addr_reg <= #1 {aw{1'b0}};`
408			`else if (ce)`
409			`addr_reg <= #1 addr;`
410
411			`//`
412			`// RAM write`
413			`//`
414			`always @(posedge clk)`
415			`if (ce && we)`
416			`mem[addr] <= #1 di;`
417
418			`endif // !OR1200_ALTERA_LPM
419			`endif // !OR1200_XILINX_RAMB16
420			`endif // !OR1200_XILINX_RAMB4
421			`endif // !OR1200_VIRTUALSILICON_SSP
422			`endif // !OR1200_VIRAGE_SSP
423			`endif // !OR1200_AVANT_ATP
424			`endif // !OR1200_ARTISAN_SSP
425
426			`endmodule`