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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x8.v] - Blame information for rev 615

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1 10 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Generic Single-Port Synchronous RAM                         ////
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////                                                              ////
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////  This file is part of memory library available from          ////
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////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
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////                                                              ////
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////  Description                                                 ////
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////  This block is a wrapper with common single-port             ////
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////  synchronous memory interface for different                  ////
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////  types of ASIC and FPGA RAMs. Beside universal memory        ////
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////  interface it also provides behavioral model of generic      ////
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////  single-port synchronous RAM.                                ////
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////  It should be used in all OPENCORES designs that want to be  ////
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////  portable accross different target technologies and          ////
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////  independent of target memory.                               ////
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////                                                              ////
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////  Supported ASIC RAMs are:                                    ////
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////  - Artisan Single-Port Sync RAM                              ////
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////  - Avant! Two-Port Sync RAM (*)                              ////
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////  - Virage Single-Port Sync RAM                               ////
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////  - Virtual Silicon Single-Port Sync RAM                      ////
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////                                                              ////
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////  Supported FPGA RAMs are:                                    ////
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////  - Xilinx Virtex RAMB16                                      ////
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////  - Xilinx Virtex RAMB4                                       ////
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////  - Altera LPM                                                ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - xilinx rams need external tri-state logic                ////
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////   - fix avant! two-port ram                                  ////
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////   - add additional RAMs                                      ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
63
//
64
// CVS Revision History
65
//
66 142 marcus.erl
// $Log: or1200_spram_2048x8.v,v $
67
// Revision 2.0  2010/06/30 11:00:00  ORSoC
68
// Minor update: 
69
// Coding style changed.
70
//
71
// Revision 1.9  2005/10/19 11:37:56  jcastillo
72
// Added support for RAMB16 Xilinx4/Spartan3 primitives
73
//
74 10 unneback
// Revision 1.8  2004/06/08 18:15:32  lampret
75
// Changed behavior of the simulation generic models
76
//
77
// Revision 1.7  2004/04/05 08:29:57  lampret
78
// Merged branch_qmem into main tree.
79
//
80
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
81
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
82
//
83
// Revision 1.3  2003/04/07 01:19:07  lampret
84
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
85
//
86
// Revision 1.2  2002/10/17 20:04:40  lampret
87
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
88
//
89
// Revision 1.1  2002/01/03 08:16:15  lampret
90
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
91
//
92
// Revision 1.8  2001/11/02 18:57:14  lampret
93
// Modified virtual silicon instantiations.
94
//
95
// Revision 1.7  2001/10/21 17:57:16  lampret
96
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
97
//
98
// Revision 1.6  2001/10/14 13:12:09  lampret
99
// MP3 version.
100
//
101
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
102
// no message
103
//
104
// Revision 1.1  2001/08/09 13:39:33  lampret
105
// Major clean-up.
106
//
107
// Revision 1.2  2001/07/30 05:38:02  lampret
108
// Adding empty directories required by HDL coding guidelines
109
//
110
//
111
 
112
// synopsys translate_off
113
`include "timescale.v"
114
// synopsys translate_on
115
`include "or1200_defines.v"
116
 
117
module or1200_spram_2048x8(
118
`ifdef OR1200_BIST
119
        // RAM BIST
120
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
121
`endif
122
        // Generic synchronous single-port RAM interface
123
        clk, rst, ce, we, oe, addr, di, doq
124
);
125
 
126
//
127
// Default address and data buses width
128
//
129
parameter aw = 11;
130
parameter dw = 8;
131
 
132
`ifdef OR1200_BIST
133
//
134
// RAM BIST
135
//
136
input mbist_si_i;
137
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
138
output mbist_so_o;
139
`endif
140
 
141
//
142
// Generic synchronous single-port RAM interface
143
//
144
input                   clk;    // Clock
145
input                   rst;    // Reset
146
input                   ce;     // Chip enable input
147
input                   we;     // Write enable input
148
input                   oe;     // Output enable input
149
input   [aw-1:0] addr;   // address bus inputs
150
input   [dw-1:0] di;     // input data bus
151
output  [dw-1:0] doq;    // output data bus
152
 
153
//
154
// Internal wires and registers
155
//
156
 
157
`ifdef OR1200_ARTISAN_SSP
158
`else
159
`ifdef OR1200_VIRTUALSILICON_SSP
160
`else
161
`ifdef OR1200_BIST
162
assign mbist_so_o = mbist_si_i;
163
`endif
164
`endif
165
`endif
166
 
167
`ifdef OR1200_ARTISAN_SSP
168
 
169
//
170
// Instantiation of ASIC memory:
171
//
172
// Artisan Synchronous Single-Port RAM (ra1sh)
173
//
174
`ifdef UNUSED
175
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(
176
`else
177
`ifdef OR1200_BIST
178
art_hssp_2048x8_bist artisan_ssp(
179
`else
180
art_hssp_2048x8 artisan_ssp(
181
`endif
182
`endif
183
`ifdef OR1200_BIST
184
        // RAM BIST
185
        .mbist_si_i(mbist_si_i),
186
        .mbist_so_o(mbist_so_o),
187
        .mbist_ctrl_i(mbist_ctrl_i),
188
`endif
189
        .CLK(clk),
190
        .CEN(~ce),
191
        .WEN(~we),
192
        .A(addr),
193
        .D(di),
194
        .OEN(~oe),
195
        .Q(doq)
196
);
197
 
198
`else
199
 
200
`ifdef OR1200_AVANT_ATP
201
 
202
//
203
// Instantiation of ASIC memory:
204
//
205
// Avant! Asynchronous Two-Port RAM
206
//
207
avant_atp avant_atp(
208
        .web(~we),
209
        .reb(),
210
        .oeb(~oe),
211
        .rcsb(),
212
        .wcsb(),
213
        .ra(addr),
214
        .wa(addr),
215
        .di(di),
216
        .doq(doq)
217
);
218
 
219
`else
220
 
221
`ifdef OR1200_VIRAGE_SSP
222
 
223
//
224
// Instantiation of ASIC memory:
225
//
226
// Virage Synchronous 1-port R/W RAM
227
//
228
virage_ssp virage_ssp(
229
        .clk(clk),
230
        .adr(addr),
231
        .d(di),
232
        .we(we),
233
        .oe(oe),
234
        .me(ce),
235
        .q(doq)
236
);
237
 
238
`else
239
 
240
`ifdef OR1200_VIRTUALSILICON_SSP
241
 
242
//
243
// Instantiation of ASIC memory:
244
//
245
// Virtual Silicon Single-Port Synchronous SRAM
246
//
247
`ifdef UNUSED
248
vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(
249
`else
250
`ifdef OR1200_BIST
251
vs_hdsp_2048x8_bist vs_ssp(
252
`else
253
vs_hdsp_2048x8 vs_ssp(
254
`endif
255
`endif
256
`ifdef OR1200_BIST
257
        // RAM BIST
258
        .mbist_si_i(mbist_si_i),
259
        .mbist_so_o(mbist_so_o),
260
        .mbist_ctrl_i(mbist_ctrl_i),
261
`endif
262
        .CK(clk),
263
        .ADR(addr),
264
        .DI(di),
265
        .WEN(~we),
266
        .CEN(~ce),
267
        .OEN(~oe),
268
        .DOUT(doq)
269
);
270
 
271
`else
272
 
273
`ifdef OR1200_XILINX_RAMB4
274
 
275
//
276
// Instantiation of FPGA memory:
277
//
278
// Virtex/Spartan2
279
//
280
 
281
//
282
// Block 0
283
//
284
RAMB4_S2 ramb4_s2_0(
285
        .CLK(clk),
286 142 marcus.erl
        .RST(1'b0),
287 10 unneback
        .ADDR(addr),
288
        .DI(di[1:0]),
289
        .EN(ce),
290
        .WE(we),
291
        .DO(doq[1:0])
292
);
293
 
294
//
295
// Block 1
296
//
297
RAMB4_S2 ramb4_s2_1(
298
        .CLK(clk),
299 142 marcus.erl
        .RST(1'b0),
300 10 unneback
        .ADDR(addr),
301
        .DI(di[3:2]),
302
        .EN(ce),
303
        .WE(we),
304
        .DO(doq[3:2])
305
);
306
 
307
//
308
// Block 2
309
//
310
RAMB4_S2 ramb4_s2_2(
311
        .CLK(clk),
312 142 marcus.erl
        .RST(1'b0),
313 10 unneback
        .ADDR(addr),
314
        .DI(di[5:4]),
315
        .EN(ce),
316
        .WE(we),
317
        .DO(doq[5:4])
318
);
319
 
320
//
321
// Block 3
322
//
323
RAMB4_S2 ramb4_s2_3(
324
        .CLK(clk),
325 142 marcus.erl
        .RST(1'b0),
326 10 unneback
        .ADDR(addr),
327
        .DI(di[7:6]),
328
        .EN(ce),
329
        .WE(we),
330
        .DO(doq[7:6])
331
);
332
 
333
`else
334
 
335
`ifdef OR1200_XILINX_RAMB16
336
 
337
//
338
// Instantiation of FPGA memory:
339
//
340
// Virtex4/Spartan3E
341
//
342
// Added By Nir Mor
343
//
344
 
345
RAMB16_S9 ramb16_s9(
346
        .CLK(clk),
347 142 marcus.erl
        .SSR(1'b0),
348 10 unneback
        .ADDR(addr),
349
        .DI(di),
350
        .DIP(1'b0),
351
        .EN(ce),
352
        .WE(we),
353
        .DO(doq),
354
        .DOP()
355
);
356
 
357
`else
358
 
359
`ifdef OR1200_ALTERA_LPM
360
 
361
//
362
// Instantiation of FPGA memory:
363
//
364
// Altera LPM
365
//
366
// Added By Jamil Khatib
367
//
368
 
369
wire    wr;
370
 
371
assign  wr = ce & we;
372
 
373
initial $display("Using Altera LPM.");
374
 
375
lpm_ram_dq lpm_ram_dq_component (
376
        .address(addr),
377
        .inclock(clk),
378
        .outclock(clk),
379
        .data(di),
380
        .we(wr),
381
        .q(doq)
382
);
383
 
384
defparam lpm_ram_dq_component.lpm_width = dw,
385
        lpm_ram_dq_component.lpm_widthad = aw,
386
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
387
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
388
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
389
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
390
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
391
 
392
`else
393
 
394
//
395
// Generic single-port synchronous RAM model
396
//
397
 
398
//
399
// Generic RAM's registers and wires
400
//
401
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
402
reg     [aw-1:0] addr_reg;               // RAM address register
403
 
404
//
405
// Data output drivers
406
//
407
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
408
 
409
//
410
// RAM address register
411
//
412 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
413
        if (rst == `OR1200_RST_VALUE)
414 258 julius
                addr_reg <=  {aw{1'b0}};
415 10 unneback
        else if (ce)
416 258 julius
                addr_reg <=  addr;
417 10 unneback
 
418
//
419
// RAM write
420
//
421
always @(posedge clk)
422
        if (ce && we)
423 258 julius
                mem[addr] <=  di;
424 10 unneback
 
425
`endif  // !OR1200_ALTERA_LPM
426
`endif  // !OR1200_XILINX_RAMB16
427
`endif  // !OR1200_XILINX_RAMB4
428
`endif  // !OR1200_VIRTUALSILICON_SSP
429
`endif  // !OR1200_VIRAGE_SSP
430
`endif  // !OR1200_AVANT_ATP
431
`endif  // !OR1200_ARTISAN_SSP
432
 
433
endmodule

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