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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_32x24.v] - Blame information for rev 53

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_32x24(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 24;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [31:24] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [31:24] unconnected;
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
`endif
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
`endif
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(rst),
        .ADDR({3'h0, addr}),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(rst),
        .ADDR({3'h0, addr}),
        .DI({8'h00, di[23:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq[23:16]})
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
RAMB16_S36 ramb16_s36(
        .CLK(clk),
        .SSR(rst),
        .ADDR({4'b0000, addr}),
        .DI({8'h00, di}),
        .DIP(4'h0),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq}),
        .DOP()
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_32x24.v] - Blame information for rev 53

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// - Altera LPM ////`
28			`//// ////`
29			`//// To Do: ////`
30			`//// - xilinx rams need external tri-state logic ////`
31			`//// - fix avant! two-port ram ////`
32			`//// - add additional RAMs ////`
33			`//// ////`
34			`//// Author(s): ////`
35			`//// - Damjan Lampret, lampret@opencores.org ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
40			`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.opencores.org/lgpl.shtml ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// CVS Revision History`
65			`//`
66			`// $Log: not supported by cvs2svn $`
67			`// Revision 1.2 2004/06/08 18:15:32 lampret`
68			`// Changed behavior of the simulation generic models`
69			`//`
70			`// Revision 1.1 2004/04/08 11:00:46 simont`
71			`// Add support for 512B instruction cache.`
72			`//`
73			`//`
74			`//`
75
76			`// synopsys translate_off`
77			`include "timescale.v"
78			`// synopsys translate_on`
79			`include "or1200_defines.v"
80
81			`module or1200_spram_32x24(`
82			`ifdef OR1200_BIST
83			`// RAM BIST`
84			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
85			`endif
86			`// Generic synchronous single-port RAM interface`
87			`clk, rst, ce, we, oe, addr, di, doq`
88			`);`
89
90			`//`
91			`// Default address and data buses width`
92			`//`
93			`parameter aw = 5;`
94			`parameter dw = 24;`
95
96			`ifdef OR1200_BIST
97			`//`
98			`// RAM BIST`
99			`//`
100			`input mbist_si_i;`
101			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
102			`output mbist_so_o;`
103			`endif
104
105			`//`
106			`// Generic synchronous single-port RAM interface`
107			`//`
108			`input clk; // Clock`
109			`input rst; // Reset`
110			`input ce; // Chip enable input`
111			`input we; // Write enable input`
112			`input oe; // Output enable input`
113			`input [aw-1:0] addr; // address bus inputs`
114			`input [dw-1:0] di; // input data bus`
115			`output [dw-1:0] doq; // output data bus`
116
117			`//`
118			`// Internal wires and registers`
119			`//`
120			`ifdef OR1200_XILINX_RAMB4
121			`wire [31:24] unconnected;`
122			`else
123			`ifdef OR1200_XILINX_RAMB16
124			`wire [31:24] unconnected;`
125			`endif // !OR1200_XILINX_RAMB16
126			`endif // !OR1200_XILINX_RAMB4
127
128			`ifdef OR1200_ARTISAN_SSP
129			`else
130			`ifdef OR1200_VIRTUALSILICON_SSP
131			`else
132			`ifdef OR1200_BIST
133			`endif
134			`endif
135			`endif
136
137			`ifdef OR1200_ARTISAN_SSP
138
139			`//`
140			`// Instantiation of ASIC memory:`
141			`//`
142			`// Artisan Synchronous Single-Port RAM (ra1sh)`
143			`//`
144			`ifdef UNUSED
145			`else
146			`ifdef OR1200_BIST
147			`else
148			`endif
149			`endif
150			`ifdef OR1200_BIST
151			`// RAM BIST`
152			`endif
153
154			`else
155
156			`ifdef OR1200_AVANT_ATP
157
158			`//`
159			`// Instantiation of ASIC memory:`
160			`//`
161			`// Avant! Asynchronous Two-Port RAM`
162			`//`
163
164			`else
165
166			`ifdef OR1200_VIRAGE_SSP
167
168			`//`
169			`// Instantiation of ASIC memory:`
170			`//`
171			`// Virage Synchronous 1-port R/W RAM`
172			`//`
173
174			`else
175
176			`ifdef OR1200_VIRTUALSILICON_SSP
177
178			`//`
179			`// Instantiation of ASIC memory:`
180			`//`
181			`// Virtual Silicon Single-Port Synchronous SRAM`
182			`//`
183			`ifdef UNUSED
184			`else
185			`ifdef OR1200_BIST
186			`else
187			`endif
188			`endif
189			`ifdef OR1200_BIST
190			`// RAM BIST`
191			`endif
192
193			`else
194
195			`ifdef OR1200_XILINX_RAMB4
196
197			`//`
198			`// Instantiation of FPGA memory:`
199			`//`
200			`// Virtex/Spartan2`
201			`//`
202
203			`//`
204			`// Block 0`
205			`//`
206			`RAMB4_S16 ramb4_s16_0(`
207			`.CLK(clk),`
208			`.RST(rst),`
209			`.ADDR({3'h0, addr}),`
210			`.DI(di[15:0]),`
211			`.EN(ce),`
212			`.WE(we),`
213			`.DO(doq[15:0])`
214			`);`
215
216			`//`
217			`// Block 1`
218			`//`
219			`RAMB4_S16 ramb4_s16_1(`
220			`.CLK(clk),`
221			`.RST(rst),`
222			`.ADDR({3'h0, addr}),`
223			`.DI({8'h00, di[23:16]}),`
224			`.EN(ce),`
225			`.WE(we),`
226			`.DO({unconnected, doq[23:16]})`
227			`);`
228
229			`else
230
231			`ifdef OR1200_XILINX_RAMB16
232
233			`//`
234			`// Instantiation of FPGA memory:`
235			`//`
236			`// Virtex4/Spartan3E`
237			`//`
238			`// Added By Nir Mor`
239			`//`
240
241			`RAMB16_S36 ramb16_s36(`
242			`.CLK(clk),`
243			`.SSR(rst),`
244			`.ADDR({4'b0000, addr}),`
245			`.DI({8'h00, di}),`
246			`.DIP(4'h0),`
247			`.EN(ce),`
248			`.WE(we),`
249			`.DO({unconnected, doq}),`
250			`.DOP()`
251			`);`
252
253			`else
254
255			`ifdef OR1200_ALTERA_LPM
256
257			`//`
258			`// Instantiation of FPGA memory:`
259			`//`
260			`// Altera LPM`
261			`//`
262			`// Added By Jamil Khatib`
263			`//`
264
265
266			`else
267
268			`//`
269			`// Generic single-port synchronous RAM model`
270			`//`
271
272			`//`
273			`// Generic RAM's registers and wires`
274			`//`
275			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
276			`reg [aw-1:0] addr_reg; // RAM address register`
277
278			`//`
279			`// Data output drivers`
280			`//`
281			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
282
283			`//`
284			`// RAM address register`
285			`//`
286			`always @(posedge clk or posedge rst)`
287			`if (rst)`
288			`addr_reg <= #1 {aw{1'b0}};`
289			`else if (ce)`
290			`addr_reg <= #1 addr;`
291
292			`//`
293			`// RAM write`
294			`//`
295			`always @(posedge clk)`
296			`if (ce && we)`
297			`mem[addr] <= #1 di;`
298
299			`endif // !OR1200_ALTERA_LPM
300			`endif // !OR1200_XILINX_RAMB16
301			`endif // !OR1200_XILINX_RAMB4
302			`endif // !OR1200_VIRTUALSILICON_SSP
303			`endif // !OR1200_VIRAGE_SSP
304			`endif // !OR1200_AVANT_ATP
305			`endif // !OR1200_ARTISAN_SSP
306
307			`endmodule`