URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_32x24.v] - Blame information for rev 797

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_32x24.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Coding style changed.
//
// Revision 1.3  2005/10/19 11:37:56  jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.2  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_32x24(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 24;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [31:24] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [31:24] unconnected;
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
`endif
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
`endif
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(1'b0),
        .ADDR({3'h0, addr}),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(1'b0),
        .ADDR({3'h0, addr}),
        .DI({8'h00, di[23:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq[23:16]})
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
RAMB16_S36 ramb16_s36(
        .CLK(clk),
        .SSR(1'b0),
        .ADDR({4'b0000, addr}),
        .DI({8'h00, di}),
        .DIP(4'h0),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq}),
        .DOP()
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                addr_reg <=  {aw{1'b0}};
        else if (ce)
                addr_reg <=  addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <=  di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_32x24.v] - Blame information for rev 797

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// - Altera LPM ////`
28			`//// ////`
29			`//// To Do: ////`
30			`//// - xilinx rams need external tri-state logic ////`
31			`//// - fix avant! two-port ram ////`
32			`//// - add additional RAMs ////`
33			`//// ////`
34			`//// Author(s): ////`
35			`//// - Damjan Lampret, lampret@opencores.org ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
40			`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.opencores.org/lgpl.shtml ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// CVS Revision History`
65			`//`
66	142	marcus.erl	`// $Log: or1200_spram_32x24.v,v $`
67			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
68			`// Minor update:`
69			`// Coding style changed.`
70			`//`
71			`// Revision 1.3 2005/10/19 11:37:56 jcastillo`
72			`// Added support for RAMB16 Xilinx4/Spartan3 primitives`
73			`//`
74	10	unneback	`// Revision 1.2 2004/06/08 18:15:32 lampret`
75			`// Changed behavior of the simulation generic models`
76			`//`
77			`// Revision 1.1 2004/04/08 11:00:46 simont`
78			`// Add support for 512B instruction cache.`
79			`//`
80			`//`
81			`//`
82
83			`// synopsys translate_off`
84			`include "timescale.v"
85			`// synopsys translate_on`
86			`include "or1200_defines.v"
87
88			`module or1200_spram_32x24(`
89			`ifdef OR1200_BIST
90			`// RAM BIST`
91			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
92			`endif
93			`// Generic synchronous single-port RAM interface`
94			`clk, rst, ce, we, oe, addr, di, doq`
95			`);`
96
97			`//`
98			`// Default address and data buses width`
99			`//`
100			`parameter aw = 5;`
101			`parameter dw = 24;`
102
103			`ifdef OR1200_BIST
104			`//`
105			`// RAM BIST`
106			`//`
107			`input mbist_si_i;`
108			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
109			`output mbist_so_o;`
110			`endif
111
112			`//`
113			`// Generic synchronous single-port RAM interface`
114			`//`
115			`input clk; // Clock`
116			`input rst; // Reset`
117			`input ce; // Chip enable input`
118			`input we; // Write enable input`
119			`input oe; // Output enable input`
120			`input [aw-1:0] addr; // address bus inputs`
121			`input [dw-1:0] di; // input data bus`
122			`output [dw-1:0] doq; // output data bus`
123
124			`//`
125			`// Internal wires and registers`
126			`//`
127			`ifdef OR1200_XILINX_RAMB4
128			`wire [31:24] unconnected;`
129			`else
130			`ifdef OR1200_XILINX_RAMB16
131			`wire [31:24] unconnected;`
132			`endif // !OR1200_XILINX_RAMB16
133			`endif // !OR1200_XILINX_RAMB4
134
135			`ifdef OR1200_ARTISAN_SSP
136			`else
137			`ifdef OR1200_VIRTUALSILICON_SSP
138			`else
139			`ifdef OR1200_BIST
140			`endif
141			`endif
142			`endif
143
144			`ifdef OR1200_ARTISAN_SSP
145
146			`//`
147			`// Instantiation of ASIC memory:`
148			`//`
149			`// Artisan Synchronous Single-Port RAM (ra1sh)`
150			`//`
151			`ifdef UNUSED
152			`else
153			`ifdef OR1200_BIST
154			`else
155			`endif
156			`endif
157			`ifdef OR1200_BIST
158			`// RAM BIST`
159			`endif
160
161			`else
162
163			`ifdef OR1200_AVANT_ATP
164
165			`//`
166			`// Instantiation of ASIC memory:`
167			`//`
168			`// Avant! Asynchronous Two-Port RAM`
169			`//`
170
171			`else
172
173			`ifdef OR1200_VIRAGE_SSP
174
175			`//`
176			`// Instantiation of ASIC memory:`
177			`//`
178			`// Virage Synchronous 1-port R/W RAM`
179			`//`
180
181			`else
182
183			`ifdef OR1200_VIRTUALSILICON_SSP
184
185			`//`
186			`// Instantiation of ASIC memory:`
187			`//`
188			`// Virtual Silicon Single-Port Synchronous SRAM`
189			`//`
190			`ifdef UNUSED
191			`else
192			`ifdef OR1200_BIST
193			`else
194			`endif
195			`endif
196			`ifdef OR1200_BIST
197			`// RAM BIST`
198			`endif
199
200			`else
201
202			`ifdef OR1200_XILINX_RAMB4
203
204			`//`
205			`// Instantiation of FPGA memory:`
206			`//`
207			`// Virtex/Spartan2`
208			`//`
209
210			`//`
211			`// Block 0`
212			`//`
213			`RAMB4_S16 ramb4_s16_0(`
214			`.CLK(clk),`
215	142	marcus.erl	`.RST(1'b0),`
216	10	unneback	`.ADDR({3'h0, addr}),`
217			`.DI(di[15:0]),`
218			`.EN(ce),`
219			`.WE(we),`
220			`.DO(doq[15:0])`
221			`);`
222
223			`//`
224			`// Block 1`
225			`//`
226			`RAMB4_S16 ramb4_s16_1(`
227			`.CLK(clk),`
228	142	marcus.erl	`.RST(1'b0),`
229	10	unneback	`.ADDR({3'h0, addr}),`
230			`.DI({8'h00, di[23:16]}),`
231			`.EN(ce),`
232			`.WE(we),`
233			`.DO({unconnected, doq[23:16]})`
234			`);`
235
236			`else
237
238			`ifdef OR1200_XILINX_RAMB16
239
240			`//`
241			`// Instantiation of FPGA memory:`
242			`//`
243			`// Virtex4/Spartan3E`
244			`//`
245			`// Added By Nir Mor`
246			`//`
247
248			`RAMB16_S36 ramb16_s36(`
249			`.CLK(clk),`
250	142	marcus.erl	`.SSR(1'b0),`
251	10	unneback	`.ADDR({4'b0000, addr}),`
252			`.DI({8'h00, di}),`
253			`.DIP(4'h0),`
254			`.EN(ce),`
255			`.WE(we),`
256			`.DO({unconnected, doq}),`
257			`.DOP()`
258			`);`
259
260			`else
261
262			`ifdef OR1200_ALTERA_LPM
263
264			`//`
265			`// Instantiation of FPGA memory:`
266			`//`
267			`// Altera LPM`
268			`//`
269			`// Added By Jamil Khatib`
270			`//`
271
272
273			`else
274
275			`//`
276			`// Generic single-port synchronous RAM model`
277			`//`
278
279			`//`
280			`// Generic RAM's registers and wires`
281			`//`
282			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
283			`reg [aw-1:0] addr_reg; // RAM address register`
284
285			`//`
286			`// Data output drivers`
287			`//`
288			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
289
290			`//`
291			`// RAM address register`
292			`//`
293	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
294			if (rst == `OR1200_RST_VALUE)
295	258	julius	`addr_reg <= {aw{1'b0}};`
296	10	unneback	`else if (ce)`
297	258	julius	`addr_reg <= addr;`
298	10	unneback
299			`//`
300			`// RAM write`
301			`//`
302			`always @(posedge clk)`
303			`if (ce && we)`
304	258	julius	`mem[addr] <= di;`
305	10	unneback
306			`endif // !OR1200_ALTERA_LPM
307			`endif // !OR1200_XILINX_RAMB16
308			`endif // !OR1200_XILINX_RAMB4
309			`endif // !OR1200_VIRTUALSILICON_SSP
310			`endif // !OR1200_VIRAGE_SSP
311			`endif // !OR1200_AVANT_ATP
312			`endif // !OR1200_ARTISAN_SSP
313
314			`endmodule`