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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_32x24.v] - Blame information for rev 10

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Generic Single-Port Synchronous RAM                         ////
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////                                                              ////
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////  This file is part of memory library available from          ////
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////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
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////                                                              ////
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////  Description                                                 ////
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////  This block is a wrapper with common single-port             ////
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////  synchronous memory interface for different                  ////
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////  types of ASIC and FPGA RAMs. Beside universal memory        ////
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////  interface it also provides behavioral model of generic      ////
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////  single-port synchronous RAM.                                ////
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////  It should be used in all OPENCORES designs that want to be  ////
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////  portable accross different target technologies and          ////
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////  independent of target memory.                               ////
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////                                                              ////
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////  Supported ASIC RAMs are:                                    ////
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////  - Artisan Single-Port Sync RAM                              ////
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////  - Avant! Two-Port Sync RAM (*)                              ////
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////  - Virage Single-Port Sync RAM                               ////
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////  - Virtual Silicon Single-Port Sync RAM                      ////
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////                                                              ////
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////  Supported FPGA RAMs are:                                    ////
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////  - Xilinx Virtex RAMB16                                      ////
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////  - Xilinx Virtex RAMB4                                       ////
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////  - Altera LPM                                                ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - xilinx rams need external tri-state logic                ////
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////   - fix avant! two-port ram                                  ////
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////   - add additional RAMs                                      ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.2  2004/06/08 18:15:32  lampret
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// Changed behavior of the simulation generic models
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//
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// Revision 1.1  2004/04/08 11:00:46  simont
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// Add support for 512B instruction cache.
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_spram_32x24(
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`ifdef OR1200_BIST
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        // RAM BIST
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        mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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        // Generic synchronous single-port RAM interface
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        clk, rst, ce, we, oe, addr, di, doq
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);
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//
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// Default address and data buses width
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//
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parameter aw = 5;
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parameter dw = 24;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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`endif
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//
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// Generic synchronous single-port RAM interface
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//
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input                   clk;    // Clock
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input                   rst;    // Reset
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input                   ce;     // Chip enable input
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input                   we;     // Write enable input
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input                   oe;     // Output enable input
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input   [aw-1:0] addr;   // address bus inputs
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input   [dw-1:0] di;     // input data bus
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output  [dw-1:0] doq;    // output data bus
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//
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// Internal wires and registers
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//
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`ifdef OR1200_XILINX_RAMB4
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wire [31:24] unconnected;
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`else
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`ifdef OR1200_XILINX_RAMB16
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wire [31:24] unconnected;
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`endif  // !OR1200_XILINX_RAMB16
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`endif  // !OR1200_XILINX_RAMB4
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`ifdef OR1200_ARTISAN_SSP
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`else
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`ifdef OR1200_VIRTUALSILICON_SSP
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`else
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`ifdef OR1200_BIST
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`endif
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`endif
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`endif
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`ifdef OR1200_ARTISAN_SSP
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//
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// Instantiation of ASIC memory:
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//
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// Artisan Synchronous Single-Port RAM (ra1sh)
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//
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`ifdef UNUSED
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`else
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`ifdef OR1200_BIST
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`else
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`endif
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`endif
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`ifdef OR1200_BIST
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        // RAM BIST
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`endif
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`else
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`ifdef OR1200_AVANT_ATP
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//
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// Instantiation of ASIC memory:
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//
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// Avant! Asynchronous Two-Port RAM
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//
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`else
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`ifdef OR1200_VIRAGE_SSP
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//
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// Instantiation of ASIC memory:
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//
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// Virage Synchronous 1-port R/W RAM
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//
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`else
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`ifdef OR1200_VIRTUALSILICON_SSP
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//
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// Instantiation of ASIC memory:
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//
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// Virtual Silicon Single-Port Synchronous SRAM
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//
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`ifdef UNUSED
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`else
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`ifdef OR1200_BIST
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`else
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`endif
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`endif
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`ifdef OR1200_BIST
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        // RAM BIST
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`endif
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`else
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`ifdef OR1200_XILINX_RAMB4
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//
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// Instantiation of FPGA memory:
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//
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// Virtex/Spartan2
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//
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//
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// Block 0
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//
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RAMB4_S16 ramb4_s16_0(
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        .CLK(clk),
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        .RST(rst),
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        .ADDR({3'h0, addr}),
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        .DI(di[15:0]),
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        .EN(ce),
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        .WE(we),
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        .DO(doq[15:0])
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);
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//
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// Block 1
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//
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RAMB4_S16 ramb4_s16_1(
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        .CLK(clk),
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        .RST(rst),
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        .ADDR({3'h0, addr}),
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        .DI({8'h00, di[23:16]}),
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        .EN(ce),
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        .WE(we),
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        .DO({unconnected, doq[23:16]})
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);
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`else
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`ifdef OR1200_XILINX_RAMB16
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//
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// Instantiation of FPGA memory:
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//
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// Virtex4/Spartan3E
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//
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// Added By Nir Mor
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//
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RAMB16_S36 ramb16_s36(
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        .CLK(clk),
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        .SSR(rst),
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        .ADDR({4'b0000, addr}),
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        .DI({8'h00, di}),
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        .DIP(4'h0),
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        .EN(ce),
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        .WE(we),
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        .DO({unconnected, doq}),
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        .DOP()
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);
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`else
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`ifdef OR1200_ALTERA_LPM
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//
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// Instantiation of FPGA memory:
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//
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// Altera LPM
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//
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// Added By Jamil Khatib
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//
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`else
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//
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// Generic single-port synchronous RAM model
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//
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//
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// Generic RAM's registers and wires
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//
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reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
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reg     [aw-1:0] addr_reg;               // RAM address register
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//
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// Data output drivers
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//
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assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
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//
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// RAM address register
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//
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always @(posedge clk or posedge rst)
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        if (rst)
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                addr_reg <= #1 {aw{1'b0}};
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        else if (ce)
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                addr_reg <= #1 addr;
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//
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// RAM write
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//
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always @(posedge clk)
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        if (ce && we)
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                mem[addr] <= #1 di;
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`endif  // !OR1200_ALTERA_LPM
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`endif  // !OR1200_XILINX_RAMB16
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`endif  // !OR1200_XILINX_RAMB4
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`endif  // !OR1200_VIRTUALSILICON_SSP
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`endif  // !OR1200_VIRAGE_SSP
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`endif  // !OR1200_AVANT_ATP
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`endif  // !OR1200_ARTISAN_SSP
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endmodule

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