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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x14.v] - Blame information for rev 110

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:41  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_64x14(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 14;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_XILINX_RAMB4
wire    [1:0]            unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire    [1:0]            unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x14 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x14_bist artisan_ssp(
`else
art_hssp_64x14 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x14 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x14_bist vs_ssp(
`else
vs_hdsp_64x14 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(rst),
        .ADDR({2'b00, addr}),
        .DI({2'b00, di[13:0]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq[13:0]})
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
 
RAMB16_S18 ramb16_s18(
        .CLK(clk),
        .SSR(rst),
        .ADDR({4'b0000, addr}),
        .DI({2'b00, di[13:0]}),
        .DIP(2'b00),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq[13:0]}),
        .DOP()
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(doq)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x14.v] - Blame information for rev 110

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// - Altera LPM ////`
28			`//// ////`
29			`//// To Do: ////`
30			`//// - xilinx rams need external tri-state logic ////`
31			`//// - fix avant! two-port ram ////`
32			`//// - add additional RAMs ////`
33			`//// ////`
34			`//// Author(s): ////`
35			`//// - Damjan Lampret, lampret@opencores.org ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
40			`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.opencores.org/lgpl.shtml ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// CVS Revision History`
65			`//`
66			`// $Log: not supported by cvs2svn $`
67			`// Revision 1.8 2004/06/08 18:15:32 lampret`
68			`// Changed behavior of the simulation generic models`
69			`//`
70			`// Revision 1.7 2004/04/05 08:29:57 lampret`
71			`// Merged branch_qmem into main tree.`
72			`//`
73			`// Revision 1.3.4.1 2003/12/09 11:46:48 simons`
74			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
75			`//`
76			`// Revision 1.3 2003/04/07 01:19:07 lampret`
77			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
78			`//`
79			`// Revision 1.2 2002/10/17 20:04:41 lampret`
80			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
81			`//`
82			`// Revision 1.1 2002/01/03 08:16:15 lampret`
83			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
84			`//`
85			`// Revision 1.7 2001/11/02 18:57:14 lampret`
86			`// Modified virtual silicon instantiations.`
87			`//`
88			`// Revision 1.6 2001/10/21 17:57:16 lampret`
89			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
90			`//`
91			`// Revision 1.5 2001/10/14 13:12:09 lampret`
92			`// MP3 version.`
93			`//`
94			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
95			`// no message`
96			`//`
97			`// Revision 1.1 2001/08/09 13:39:33 lampret`
98			`// Major clean-up.`
99			`//`
100			`// Revision 1.2 2001/07/30 05:38:02 lampret`
101			`// Adding empty directories required by HDL coding guidelines`
102			`//`
103			`//`
104
105			`// synopsys translate_off`
106			`include "timescale.v"
107			`// synopsys translate_on`
108			`include "or1200_defines.v"
109
110			`module or1200_spram_64x14(`
111			`ifdef OR1200_BIST
112			`// RAM BIST`
113			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
114			`endif
115			`// Generic synchronous single-port RAM interface`
116			`clk, rst, ce, we, oe, addr, di, doq`
117			`);`
118
119			`//`
120			`// Default address and data buses width`
121			`//`
122			`parameter aw = 6;`
123			`parameter dw = 14;`
124
125			`ifdef OR1200_BIST
126			`//`
127			`// RAM BIST`
128			`//`
129			`input mbist_si_i;`
130			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
131			`output mbist_so_o;`
132			`endif
133
134			`//`
135			`// Generic synchronous single-port RAM interface`
136			`//`
137			`input clk; // Clock`
138			`input rst; // Reset`
139			`input ce; // Chip enable input`
140			`input we; // Write enable input`
141			`input oe; // Output enable input`
142			`input [aw-1:0] addr; // address bus inputs`
143			`input [dw-1:0] di; // input data bus`
144			`output [dw-1:0] doq; // output data bus`
145
146			`//`
147			`// Internal wires and registers`
148			`//`
149
150			`ifdef OR1200_XILINX_RAMB4
151			`wire [1:0] unconnected;`
152			`else
153			`ifdef OR1200_XILINX_RAMB16
154			`wire [1:0] unconnected;`
155			`endif // !OR1200_XILINX_RAMB16
156			`endif // !OR1200_XILINX_RAMB4
157
158			`ifdef OR1200_ARTISAN_SSP
159			`else
160			`ifdef OR1200_VIRTUALSILICON_SSP
161			`else
162			`ifdef OR1200_BIST
163			`assign mbist_so_o = mbist_si_i;`
164			`endif
165			`endif
166			`endif
167
168			`ifdef OR1200_ARTISAN_SSP
169
170			`//`
171			`// Instantiation of ASIC memory:`
172			`//`
173			`// Artisan Synchronous Single-Port RAM (ra1sh)`
174			`//`
175			`ifdef UNUSED
176			`art_hssp_64x14 #(dw, 1<<aw, aw) artisan_ssp(`
177			`else
178			`ifdef OR1200_BIST
179			`art_hssp_64x14_bist artisan_ssp(`
180			`else
181			`art_hssp_64x14 artisan_ssp(`
182			`endif
183			`endif
184			`ifdef OR1200_BIST
185			`// RAM BIST`
186			`.mbist_si_i(mbist_si_i),`
187			`.mbist_so_o(mbist_so_o),`
188			`.mbist_ctrl_i(mbist_ctrl_i),`
189			`endif
190			`.CLK(clk),`
191			`.CEN(~ce),`
192			`.WEN(~we),`
193			`.A(addr),`
194			`.D(di),`
195			`.OEN(~oe),`
196			`.Q(doq)`
197			`);`
198
199			`else
200
201			`ifdef OR1200_AVANT_ATP
202
203			`//`
204			`// Instantiation of ASIC memory:`
205			`//`
206			`// Avant! Asynchronous Two-Port RAM`
207			`//`
208			`avant_atp avant_atp(`
209			`.web(~we),`
210			`.reb(),`
211			`.oeb(~oe),`
212			`.rcsb(),`
213			`.wcsb(),`
214			`.ra(addr),`
215			`.wa(addr),`
216			`.di(di),`
217			`.doq(doq)`
218			`);`
219
220			`else
221
222			`ifdef OR1200_VIRAGE_SSP
223
224			`//`
225			`// Instantiation of ASIC memory:`
226			`//`
227			`// Virage Synchronous 1-port R/W RAM`
228			`//`
229			`virage_ssp virage_ssp(`
230			`.clk(clk),`
231			`.adr(addr),`
232			`.d(di),`
233			`.we(we),`
234			`.oe(oe),`
235			`.me(ce),`
236			`.q(doq)`
237			`);`
238
239			`else
240
241			`ifdef OR1200_VIRTUALSILICON_SSP
242
243			`//`
244			`// Instantiation of ASIC memory:`
245			`//`
246			`// Virtual Silicon Single-Port Synchronous SRAM`
247			`//`
248			`ifdef UNUSED
249			`vs_hdsp_64x14 #(1<<aw, aw-1, dw-1) vs_ssp(`
250			`else
251			`ifdef OR1200_BIST
252			`vs_hdsp_64x14_bist vs_ssp(`
253			`else
254			`vs_hdsp_64x14 vs_ssp(`
255			`endif
256			`endif
257			`ifdef OR1200_BIST
258			`// RAM BIST`
259			`.mbist_si_i(mbist_si_i),`
260			`.mbist_so_o(mbist_so_o),`
261			`.mbist_ctrl_i(mbist_ctrl_i),`
262			`endif
263			`.CK(clk),`
264			`.ADR(addr),`
265			`.DI(di),`
266			`.WEN(~we),`
267			`.CEN(~ce),`
268			`.OEN(~oe),`
269			`.DOUT(doq)`
270			`);`
271
272			`else
273
274			`ifdef OR1200_XILINX_RAMB4
275
276			`//`
277			`// Instantiation of FPGA memory:`
278			`//`
279			`// Virtex/Spartan2`
280			`//`
281
282			`//`
283			`// Block 0`
284			`//`
285			`RAMB4_S16 ramb4_s16_0(`
286			`.CLK(clk),`
287			`.RST(rst),`
288			`.ADDR({2'b00, addr}),`
289			`.DI({2'b00, di[13:0]}),`
290			`.EN(ce),`
291			`.WE(we),`
292			`.DO({unconnected, doq[13:0]})`
293			`);`
294
295			`else
296
297			`ifdef OR1200_XILINX_RAMB16
298
299			`//`
300			`// Instantiation of FPGA memory:`
301			`//`
302			`// Virtex4/Spartan3E`
303			`//`
304
305			`RAMB16_S18 ramb16_s18(`
306			`.CLK(clk),`
307			`.SSR(rst),`
308			`.ADDR({4'b0000, addr}),`
309			`.DI({2'b00, di[13:0]}),`
310			`.DIP(2'b00),`
311			`.EN(ce),`
312			`.WE(we),`
313			`.DO({unconnected, doq[13:0]}),`
314			`.DOP()`
315			`);`
316
317			`else
318
319			`ifdef OR1200_ALTERA_LPM
320
321			`//`
322			`// Instantiation of FPGA memory:`
323			`//`
324			`// Altera LPM`
325			`//`
326			`// Added By Jamil Khatib`
327			`//`
328
329			`wire wr;`
330
331			`assign wr = ce & we;`
332
333			`initial $display("Using Altera LPM.");`
334
335			`lpm_ram_dq lpm_ram_dq_component (`
336			`.address(addr),`
337			`.inclock(clk),`
338			`.outclock(clk),`
339			`.data(di),`
340			`.we(wr),`
341			`.q(doq)`
342			`);`
343
344			`defparam lpm_ram_dq_component.lpm_width = dw,`
345			`lpm_ram_dq_component.lpm_widthad = aw,`
346			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
347			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
348			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
349			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
350			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
351
352			`else
353
354			`//`
355			`// Generic single-port synchronous RAM model`
356			`//`
357
358			`//`
359			`// Generic RAM's registers and wires`
360			`//`
361			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
362			`reg [aw-1:0] addr_reg; // RAM address register`
363
364			`//`
365			`// Data output drivers`
366			`//`
367			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
368
369			`//`
370			`// RAM address register`
371			`//`
372			`always @(posedge clk or posedge rst)`
373			`if (rst)`
374			`addr_reg <= #1 {aw{1'b0}};`
375			`else if (ce)`
376			`addr_reg <= #1 addr;`
377
378			`//`
379			`// RAM write`
380			`//`
381			`always @(posedge clk)`
382			`if (ce && we)`
383			`mem[addr] <= #1 di;`
384
385			`endif // !OR1200_ALTERA_LPM
386			`endif // !OR1200_XILINX_RAMB16
387			`endif // !OR1200_XILINX_RAMB4
388			`endif // !OR1200_VIRTUALSILICON_SSP
389			`endif // !OR1200_VIRAGE_SSP
390			`endif // !OR1200_AVANT_ATP
391			`endif // !OR1200_ARTISAN_SSP
392
393			`endmodule`