OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Blame information for rev 767

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Generic Single-Port Synchronous RAM                         ////
4
////                                                              ////
5
////  This file is part of memory library available from          ////
6
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  This block is a wrapper with common single-port             ////
10
////  synchronous memory interface for different                  ////
11
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
12
////  interface it also provides behavioral model of generic      ////
13
////  single-port synchronous RAM.                                ////
14
////  It should be used in all OPENCORES designs that want to be  ////
15
////  portable accross different target technologies and          ////
16
////  independent of target memory.                               ////
17
////                                                              ////
18
////  Supported ASIC RAMs are:                                    ////
19
////  - Artisan Single-Port Sync RAM                              ////
20
////  - Avant! Two-Port Sync RAM (*)                              ////
21
////  - Virage Single-Port Sync RAM                               ////
22
////  - Virtual Silicon Single-Port Sync RAM                      ////
23
////                                                              ////
24
////  Supported FPGA RAMs are:                                    ////
25
////  - Xilinx Virtex RAMB16                                      ////
26
////  - Xilinx Virtex RAMB4                                       ////
27
////  - Altera LPM                                                ////
28
////                                                              ////
29
////  To Do:                                                      ////
30
////   - xilinx rams need external tri-state logic                ////
31
////   - fix avant! two-port ram                                  ////
32
////   - add additional RAMs                                      ////
33
////                                                              ////
34
////  Author(s):                                                  ////
35
////      - Damjan Lampret, lampret@opencores.org                 ////
36
////                                                              ////
37
//////////////////////////////////////////////////////////////////////
38
////                                                              ////
39
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
40
////                                                              ////
41
//// This source file may be used and distributed without         ////
42
//// restriction provided that this copyright statement is not    ////
43
//// removed from the file and that any derivative work contains  ////
44
//// the original copyright notice and the associated disclaimer. ////
45
////                                                              ////
46
//// This source file is free software; you can redistribute it   ////
47
//// and/or modify it under the terms of the GNU Lesser General   ////
48
//// Public License as published by the Free Software Foundation; ////
49
//// either version 2.1 of the License, or (at your option) any   ////
50
//// later version.                                               ////
51
////                                                              ////
52
//// This source is distributed in the hope that it will be       ////
53
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
54
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
55
//// PURPOSE.  See the GNU Lesser General Public License for more ////
56
//// details.                                                     ////
57
////                                                              ////
58
//// You should have received a copy of the GNU Lesser General    ////
59
//// Public License along with this source; if not, download it   ////
60
//// from http://www.opencores.org/lgpl.shtml                     ////
61
////                                                              ////
62
//////////////////////////////////////////////////////////////////////
63
//
64
// CVS Revision History
65
//
66 142 marcus.erl
// $Log: or1200_spram_64x24.v,v $
67
// Revision 2.0  2010/06/30 11:00:00  ORSoC
68
// Minor update: 
69
// Coding style changed.
70
//
71
// Revision 1.9  2005/10/19 11:37:56  jcastillo
72
// Added support for RAMB16 Xilinx4/Spartan3 primitives
73
//
74 10 unneback
// Revision 1.8  2004/06/08 18:15:32  lampret
75
// Changed behavior of the simulation generic models
76
//
77
// Revision 1.7  2004/04/05 08:29:57  lampret
78
// Merged branch_qmem into main tree.
79
//
80
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
81
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
82
//
83
// Revision 1.3  2003/04/07 01:19:07  lampret
84
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
85
//
86
// Revision 1.2  2002/10/17 20:04:41  lampret
87
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
88
//
89
// Revision 1.1  2002/01/03 08:16:15  lampret
90
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
91
//
92
// Revision 1.8  2001/11/02 18:57:14  lampret
93
// Modified virtual silicon instantiations.
94
//
95
// Revision 1.7  2001/10/22 19:39:56  lampret
96
// Fixed parameters in generic sprams.
97
//
98
// Revision 1.6  2001/10/21 17:57:16  lampret
99
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
100
//
101
// Revision 1.5  2001/10/14 13:12:09  lampret
102
// MP3 version.
103
//
104
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
105
// no message
106
//
107
// Revision 1.1  2001/08/09 13:39:33  lampret
108
// Major clean-up.
109
//
110
// Revision 1.2  2001/07/30 05:38:02  lampret
111
// Adding empty directories required by HDL coding guidelines
112
//
113
//
114
 
115
// synopsys translate_off
116
`include "timescale.v"
117
// synopsys translate_on
118
`include "or1200_defines.v"
119
 
120
module or1200_spram_64x24(
121
`ifdef OR1200_BIST
122
        // RAM BIST
123
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
124
`endif
125
        // Generic synchronous single-port RAM interface
126
        clk, rst, ce, we, oe, addr, di, doq
127
);
128
 
129
//
130
// Default address and data buses width
131
//
132
parameter aw = 6;
133
parameter dw = 24;
134
 
135
`ifdef OR1200_BIST
136
//
137
// RAM BIST
138
//
139
input mbist_si_i;
140
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
141
output mbist_so_o;
142
`endif
143
 
144
//
145
// Generic synchronous single-port RAM interface
146
//
147
input                   clk;    // Clock
148
input                   rst;    // Reset
149
input                   ce;     // Chip enable input
150
input                   we;     // Write enable input
151
input                   oe;     // Output enable input
152
input   [aw-1:0] addr;   // address bus inputs
153
input   [dw-1:0] di;     // input data bus
154
output  [dw-1:0] doq;    // output data bus
155
 
156
//
157
// Internal wires and registers
158
//
159
`ifdef OR1200_XILINX_RAMB4
160
wire    [7:0]            unconnected;
161
`else
162
`ifdef OR1200_XILINX_RAMB16
163
wire    [7:0]            unconnected;
164
`endif // !OR1200_XILINX_RAMB16
165
`endif // !OR1200_XILINX_RAMB4
166
 
167
`ifdef OR1200_ARTISAN_SSP
168
`else
169
`ifdef OR1200_VIRTUALSILICON_SSP
170
`else
171
`ifdef OR1200_BIST
172
assign mbist_so_o = mbist_si_i;
173
`endif
174
`endif
175
`endif
176
 
177
`ifdef OR1200_ARTISAN_SSP
178
 
179
//
180
// Instantiation of ASIC memory:
181
//
182
// Artisan Synchronous Single-Port RAM (ra1sh)
183
//
184
`ifdef UNUSED
185
art_hssp_64x24 #(dw, 1<<aw, aw) artisan_ssp(
186
`else
187
`ifdef OR1200_BIST
188
art_hssp_64x24_bist artisan_ssp(
189
`else
190
art_hssp_64x24 artisan_ssp(
191
`endif
192
`endif
193
`ifdef OR1200_BIST
194
        // RAM BIST
195
        .mbist_si_i(mbist_si_i),
196
        .mbist_so_o(mbist_so_o),
197
        .mbist_ctrl_i(mbist_ctrl_i),
198
`endif
199
        .CLK(clk),
200
        .CEN(~ce),
201
        .WEN(~we),
202
        .A(addr),
203
        .D(di),
204
        .OEN(~oe),
205
        .Q(doq)
206
);
207
 
208
`else
209
 
210
`ifdef OR1200_AVANT_ATP
211
 
212
//
213
// Instantiation of ASIC memory:
214
//
215
// Avant! Asynchronous Two-Port RAM
216
//
217
avant_atp avant_atp(
218
        .web(~we),
219
        .reb(),
220
        .oeb(~oe),
221
        .rcsb(),
222
        .wcsb(),
223
        .ra(addr),
224
        .wa(addr),
225
        .di(di),
226
        .doq(doq)
227
);
228
 
229
`else
230
 
231
`ifdef OR1200_VIRAGE_SSP
232
 
233
//
234
// Instantiation of ASIC memory:
235
//
236
// Virage Synchronous 1-port R/W RAM
237
//
238
virage_ssp virage_ssp(
239
        .clk(clk),
240
        .adr(addr),
241
        .d(di),
242
        .we(we),
243
        .oe(oe),
244
        .me(ce),
245
        .q(doq)
246
);
247
 
248
`else
249
 
250
`ifdef OR1200_VIRTUALSILICON_SSP
251
 
252
//
253
// Instantiation of ASIC memory:
254
//
255
// Virtual Silicon Single-Port Synchronous SRAM
256
//
257
`ifdef UNUSED
258
vs_hdsp_64x24 #(1<<aw, aw-1, dw-1) vs_ssp(
259
`else
260
`ifdef OR1200_BIST
261
vs_hdsp_64x24_bist vs_ssp(
262
`else
263
vs_hdsp_64x24 vs_ssp(
264
`endif
265
`endif
266
`ifdef OR1200_BIST
267
        // RAM BIST
268
        .mbist_si_i(mbist_si_i),
269
        .mbist_so_o(mbist_so_o),
270
        .mbist_ctrl_i(mbist_ctrl_i),
271
`endif
272
        .CK(clk),
273
        .ADR(addr),
274
        .DI(di),
275
        .WEN(~we),
276
        .CEN(~ce),
277
        .OEN(~oe),
278
        .DOUT(doq)
279
);
280
 
281
`else
282
 
283
`ifdef OR1200_XILINX_RAMB4
284
 
285
//
286
// Instantiation of FPGA memory:
287
//
288
// Virtex/Spartan2
289
//
290
 
291
//
292
// Block 0
293
//
294
RAMB4_S16 ramb4_s16_0(
295
        .CLK(clk),
296 142 marcus.erl
        .RST(1'b0),
297 10 unneback
        .ADDR({2'b00, addr}),
298
        .DI(di[15:0]),
299
        .EN(ce),
300
        .WE(we),
301
        .DO(doq[15:0])
302
);
303
 
304
//
305
// Block 1
306
//
307
RAMB4_S16 ramb4_s16_1(
308
        .CLK(clk),
309 142 marcus.erl
        .RST(1'b0),
310 10 unneback
        .ADDR({2'b00, addr}),
311
        .DI({8'h00, di[23:16]}),
312
        .EN(ce),
313
        .WE(we),
314
        .DO({unconnected, doq[23:16]})
315
);
316
 
317
`else
318
 
319
`ifdef OR1200_XILINX_RAMB16
320
 
321
//
322
// Instantiation of FPGA memory:
323
//
324
// Virtex4/Spartan3E
325
//
326
// Added By Nir Mor
327
//
328
 
329
RAMB16_S36 ramb16_s36(
330
        .CLK(clk),
331 142 marcus.erl
        .SSR(1'b0),
332 10 unneback
        .ADDR({3'b000, addr}),
333
        .DI({8'h00,di}),
334
        .DIP(4'h0),
335
        .EN(ce),
336
        .WE(we),
337
        .DO({unconnected, doq}),
338
        .DOP()
339
);
340
 
341
`else
342
 
343
`ifdef OR1200_ALTERA_LPM
344
 
345
//
346
// Instantiation of FPGA memory:
347
//
348
// Altera LPM
349
//
350
// Added By Jamil Khatib
351
//
352
 
353
wire    wr;
354
 
355
assign  wr = ce & we;
356
 
357
initial $display("Using Altera LPM.");
358
 
359
lpm_ram_dq lpm_ram_dq_component (
360
        .address(addr),
361
        .inclock(clk),
362
        .outclock(clk),
363
        .data(di),
364
        .we(wr),
365
        .q(doq)
366
);
367
 
368
defparam lpm_ram_dq_component.lpm_width = dw,
369
        lpm_ram_dq_component.lpm_widthad = aw,
370
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
371
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
372
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
373
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
374
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
375
 
376
`else
377
 
378
//
379
// Generic single-port synchronous RAM model
380
//
381
 
382
//
383
// Generic RAM's registers and wires
384
//
385
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
386
reg     [aw-1:0] addr_reg;               // RAM address register
387
 
388
//
389
// Data output drivers
390
//
391
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
392
 
393
//
394
// RAM address register
395
//
396 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
397
        if (rst == `OR1200_RST_VALUE)
398 258 julius
                addr_reg <=  {aw{1'b0}};
399 10 unneback
        else if (ce)
400 258 julius
                addr_reg <=  addr;
401 10 unneback
 
402
//
403
// RAM write
404
//
405
always @(posedge clk)
406
        if (ce && we)
407 258 julius
                mem[addr] <=  di;
408 10 unneback
 
409
`endif  // !OR1200_ALTERA_LPM
410
`endif  // !OR1200_XILINX_RAMB16
411
`endif  // !OR1200_XILINX_RAMB4
412
`endif  // !OR1200_VIRTUALSILICON_SSP
413
`endif  // !OR1200_VIRAGE_SSP
414
`endif  // !OR1200_AVANT_ATP
415
`endif  // !OR1200_ARTISAN_SSP
416
 
417
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.