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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Blame information for rev 151

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  OR1200's interface to SPRs                                  ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
9
////  Decoding of SPR addresses and access to SPRs                ////
10
////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46 142 marcus.erl
// $Log: or1200_sprs.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// Major update: 
49
// Structure reordered and bugs fixed. 
50
//
51
// Revision 1.11  2004/04/05 08:29:57  lampret
52
// Merged branch_qmem into main tree.
53
//
54 10 unneback
// Revision 1.9.4.1  2003/12/17 13:43:38  simons
55
// Exception prefix configuration changed.
56
//
57
// Revision 1.9  2002/09/07 05:42:02  lampret
58
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
59
//
60
// Revision 1.8  2002/08/28 01:44:25  lampret
61
// Removed some commented RTL. Fixed SR/ESR flag bug.
62
//
63
// Revision 1.7  2002/03/29 15:16:56  lampret
64
// Some of the warnings fixed.
65
//
66
// Revision 1.6  2002/03/11 01:26:57  lampret
67
// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
68
//
69
// Revision 1.5  2002/02/01 19:56:54  lampret
70
// Fixed combinational loops.
71
//
72
// Revision 1.4  2002/01/23 07:52:36  lampret
73
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
74
//
75
// Revision 1.3  2002/01/19 09:27:49  lampret
76
// SR[TEE] should be zero after reset.
77
//
78
// Revision 1.2  2002/01/18 07:56:00  lampret
79
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
80
//
81
// Revision 1.1  2002/01/03 08:16:15  lampret
82
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
83
//
84
// Revision 1.12  2001/11/23 21:42:31  simons
85
// Program counter divided to PPC and NPC.
86
//
87
// Revision 1.11  2001/11/23 08:38:51  lampret
88
// Changed DSR/DRR behavior and exception detection.
89
//
90
// Revision 1.10  2001/11/12 01:45:41  lampret
91
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
92
//
93
// Revision 1.9  2001/10/21 17:57:16  lampret
94
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
95
//
96
// Revision 1.8  2001/10/14 13:12:10  lampret
97
// MP3 version.
98
//
99
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
100
// no message
101
//
102
// Revision 1.3  2001/08/13 03:36:20  lampret
103
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
104
//
105
// Revision 1.2  2001/08/09 13:39:33  lampret
106
// Major clean-up.
107
//
108
// Revision 1.1  2001/07/20 00:46:21  lampret
109
// Development version of RTL. Libraries are missing.
110
//
111
//
112
 
113
// synopsys translate_off
114
`include "timescale.v"
115
// synopsys translate_on
116
`include "or1200_defines.v"
117
 
118
module or1200_sprs(
119
                // Clk & Rst
120
                clk, rst,
121
 
122
                // Internal CPU interface
123
                flagforw, flag_we, flag, cyforw, cy_we, carry,
124 142 marcus.erl
                addrbase, addrofs, dat_i, branch_op, ex_spr_read, ex_spr_write,
125 10 unneback
                epcr, eear, esr, except_started,
126
                to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
127
                spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
128 142 marcus.erl
                boot_adr_sel_i,
129 10 unneback
 
130
                // From/to other RISC units
131
                spr_dat_pic, spr_dat_tt, spr_dat_pm,
132
                spr_dat_dmmu, spr_dat_immu, spr_dat_du,
133
                spr_addr, spr_dat_o, spr_cs, spr_we,
134
 
135
                du_addr, du_dat_du, du_read,
136
                du_write, du_dat_cpu
137
 
138
);
139
 
140
parameter width = `OR1200_OPERAND_WIDTH;
141
 
142
//
143
// I/O Ports
144
//
145
 
146
//
147
// Internal CPU interface
148
//
149
input                           clk;            // Clock
150
input                           rst;            // Reset
151
input                           flagforw;       // From ALU
152
input                           flag_we;        // From ALU
153
output                          flag;           // SR[F]
154
input                           cyforw;         // From ALU
155
input                           cy_we;          // From ALU
156
output                          carry;          // SR[CY]
157
input   [width-1:0]              addrbase;       // SPR base address
158
input   [15:0]                   addrofs;        // SPR offset
159
input   [width-1:0]              dat_i;          // SPR write data
160 142 marcus.erl
input                           ex_spr_read;    // l.mfspr in EX
161
input                           ex_spr_write;   // l.mtspr in EX
162 10 unneback
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch operation
163
input   [width-1:0]              epcr;           // EPCR0
164
input   [width-1:0]              eear;           // EEAR0
165
input   [`OR1200_SR_WIDTH-1:0]   esr;            // ESR0
166
input                           except_started; // Exception was started
167
output  [width-1:0]              to_wbmux;       // For l.mfspr
168
output                          epcr_we;        // EPCR0 write enable
169
output                          eear_we;        // EEAR0 write enable
170
output                          esr_we;         // ESR0 write enable
171
output                          pc_we;          // PC write enable
172
output                          sr_we;          // Write enable SR
173
output  [`OR1200_SR_WIDTH-1:0]   to_sr;          // Data to SR
174
output  [`OR1200_SR_WIDTH-1:0]   sr;             // SR
175
input   [31:0]                   spr_dat_cfgr;   // Data from CFGR
176
input   [31:0]                   spr_dat_rf;     // Data from RF
177
input   [31:0]                   spr_dat_npc;    // Data from NPC
178
input   [31:0]                   spr_dat_ppc;    // Data from PPC   
179
input   [31:0]                   spr_dat_mac;    // Data from MAC
180 142 marcus.erl
input                           boot_adr_sel_i;
181 10 unneback
 
182
//
183
// To/from other RISC units
184
//
185
input   [31:0]                   spr_dat_pic;    // Data from PIC
186
input   [31:0]                   spr_dat_tt;     // Data from TT
187
input   [31:0]                   spr_dat_pm;     // Data from PM
188
input   [31:0]                   spr_dat_dmmu;   // Data from DMMU
189
input   [31:0]                   spr_dat_immu;   // Data from IMMU
190
input   [31:0]                   spr_dat_du;     // Data from DU
191
output  [31:0]                   spr_addr;       // SPR Address
192
output  [31:0]                   spr_dat_o;      // Data to unit
193
output  [31:0]                   spr_cs;         // Unit select
194
output                          spr_we;         // SPR write enable
195
 
196
//
197
// To/from Debug Unit
198
//
199
input   [width-1:0]              du_addr;        // Address
200
input   [width-1:0]              du_dat_du;      // Data from DU to SPRS
201
input                           du_read;        // Read qualifier
202
input                           du_write;       // Write qualifier
203
output  [width-1:0]              du_dat_cpu;     // Data from SPRS to DU
204
 
205
//
206
// Internal regs & wires
207
//
208 142 marcus.erl
reg     [`OR1200_SR_WIDTH-1:0]   sr_reg;                 // SR
209
reg                             sr_reg_bit_eph;         // SR_EPH bit
210
reg                             sr_reg_bit_eph_select;  // SR_EPH select
211
wire                            sr_reg_bit_eph_muxed;   // SR_EPH muxed bit
212
reg     [`OR1200_SR_WIDTH-1:0]   sr;                     // SR
213 10 unneback
reg     [width-1:0]              to_wbmux;       // For l.mfspr
214
wire                            cfgr_sel;       // Select for cfg regs
215
wire                            rf_sel;         // Select for RF
216
wire                            npc_sel;        // Select for NPC
217
wire                            ppc_sel;        // Select for PPC
218
wire                            sr_sel;         // Select for SR        
219
wire                            epcr_sel;       // Select for EPCR0
220
wire                            eear_sel;       // Select for EEAR0
221
wire                            esr_sel;        // Select for ESR0
222
wire    [31:0]                   sys_data;       // Read data from system SPRs
223
wire                            du_access;      // Debug unit access
224
reg     [31:0]                   unqualified_cs; // Unqualified chip selects
225 142 marcus.erl
   wire                         ex_spr_write; // jb
226
 
227 10 unneback
//
228
// Decide if it is debug unit access
229
//
230
assign du_access = du_read | du_write;
231
 
232
//
233
// Generate SPR address from base address and offset
234
// OR from debug unit address
235
//
236 142 marcus.erl
assign spr_addr = du_access ? du_addr : (addrbase | {16'h0000, addrofs});
237 10 unneback
 
238
//
239
// SPR is written by debug unit or by l.mtspr
240
//
241
assign spr_dat_o = du_write ? du_dat_du : dat_i;
242
 
243
//
244
// debug unit data input:
245 142 marcus.erl
//  - read of SPRS by debug unit
246 10 unneback
//  - write into debug unit SPRs by debug unit itself
247
//  - write into debug unit SPRs by l.mtspr
248
//
249 142 marcus.erl
assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;
250 10 unneback
 
251
//
252 142 marcus.erl
// Write into SPRs when DU or l.mtspr
253 10 unneback
//
254 151 marcus.erl
assign spr_we = du_write | ( ex_spr_write & !du_access );
255 10 unneback
 
256 151 marcus.erl
 
257 10 unneback
//
258
// Qualify chip selects
259
//
260 142 marcus.erl
assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & sr[`OR1200_SR_SM])}};
261 10 unneback
 
262
//
263
// Decoding of groups
264
//
265
always @(spr_addr)
266
        case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
267
                `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
268
                `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
269
                `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
270
                `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
271
                `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
272
                `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
273
                `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
274
                `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
275
                `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
276
                `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
277
                `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
278
                `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
279
                `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
280
                `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
281
                `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
282
                `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
283
                `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
284
                `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
285
                `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
286
                `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
287
                `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
288
                `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
289
                `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
290
                `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
291
                `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
292
                `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
293
                `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
294
                `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
295
                `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
296
                `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
297
                `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
298
                `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
299
        endcase
300
 
301
//
302
// SPRs System Group
303
//
304
 
305
//
306
// What to write into SR
307
//
308
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
309 142 marcus.erl
                (except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
310 10 unneback
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
311 142 marcus.erl
                (spr_we && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
312 10 unneback
                sr[`OR1200_SR_FO:`OR1200_SR_OV];
313 142 marcus.erl
assign to_sr[`OR1200_SR_TED] =
314
                (except_started) ? 1'b1 :
315
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
316
                (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED]:
317
                sr[`OR1200_SR_TED];
318 10 unneback
assign to_sr[`OR1200_SR_CY] =
319 142 marcus.erl
                (except_started) ? sr[`OR1200_SR_CY] :
320 10 unneback
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
321
                cy_we ? cyforw :
322 142 marcus.erl
                (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
323 10 unneback
                sr[`OR1200_SR_CY];
324
assign to_sr[`OR1200_SR_F] =
325 142 marcus.erl
                (except_started) ? sr[`OR1200_SR_F] :
326 10 unneback
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
327
                flag_we ? flagforw :
328 142 marcus.erl
                (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
329 10 unneback
                sr[`OR1200_SR_F];
330
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
331 142 marcus.erl
                (except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00, sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
332 10 unneback
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
333 142 marcus.erl
                (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
334 10 unneback
                sr[`OR1200_SR_CE:`OR1200_SR_SM];
335
 
336
//
337
// Selects for system SPRs
338
//
339
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
340
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
341
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
342
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
343
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
344
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
345
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
346
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
347
 
348
//
349
// Write enables for system SPRs
350
//
351 142 marcus.erl
assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
352
assign pc_we = (du_write && (npc_sel | ppc_sel));
353
assign epcr_we = (spr_we && epcr_sel);
354
assign eear_we = (spr_we && eear_sel);
355
assign esr_we = (spr_we && esr_sel);
356 10 unneback
 
357
//
358
// Output from system SPRs
359
//
360 142 marcus.erl
assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
361
                  (spr_dat_rf & {32{rf_sel}}) |
362
                  (spr_dat_npc & {32{npc_sel}}) |
363
                  (spr_dat_ppc & {32{ppc_sel}}) |
364
                  ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
365
                  (epcr & {32{epcr_sel}}) |
366
                  (eear & {32{eear_sel}}) |
367
                  ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
368 10 unneback
 
369
//
370
// Flag alias
371
//
372
assign flag = sr[`OR1200_SR_F];
373
 
374
//
375
// Carry alias
376
//
377
assign carry = sr[`OR1200_SR_CY];
378
 
379
//
380
// Supervision register
381
//
382
always @(posedge clk or posedge rst)
383
        if (rst)
384 142 marcus.erl
                sr_reg <= #1 {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
385
        else if (except_started)
386
                sr_reg <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
387 10 unneback
        else if (sr_we)
388 142 marcus.erl
                sr_reg <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
389 10 unneback
 
390 142 marcus.erl
// EPH part of Supervision register
391
always @(posedge clk or posedge rst)
392
        // default value 
393
        if (rst) begin
394
                sr_reg_bit_eph <= #1 `OR1200_SR_EPH_DEF;
395
                sr_reg_bit_eph_select <= #1 1'b1;       // select async. value due to reset state
396
        end
397
        // selected value (different from default) is written into FF after reset state
398
        else if (sr_reg_bit_eph_select) begin
399
                sr_reg_bit_eph <= #1 boot_adr_sel_i;    // dynamic value can only be assigned to FF out of reset! 
400
                sr_reg_bit_eph_select <= #1 1'b0;       // select FF value 
401
        end
402
        else if (sr_we) begin
403
                sr_reg_bit_eph <= #1 to_sr[`OR1200_SR_EPH];
404
        end
405
 
406
// select async. value of EPH bit after reset 
407
assign  sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ? boot_adr_sel_i : sr_reg_bit_eph;
408
 
409
// EPH part joined together with rest of Supervision register
410
always @(sr_reg or sr_reg_bit_eph_muxed)
411
        sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed, sr_reg[`OR1200_SR_WIDTH-4:0]};
412
 
413 10 unneback
//
414
// MTSPR/MFSPR interface
415
//
416 142 marcus.erl
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
417 10 unneback
        spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
418 142 marcus.erl
                casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
419
                        `OR1200_SPR_GROUP_SYS:
420
                                to_wbmux = sys_data;
421
                        `OR1200_SPR_GROUP_TT:
422
                                to_wbmux = spr_dat_tt;
423
                        `OR1200_SPR_GROUP_PIC:
424
                                to_wbmux = spr_dat_pic;
425
                        `OR1200_SPR_GROUP_PM:
426
                                to_wbmux = spr_dat_pm;
427
                        `OR1200_SPR_GROUP_DMMU:
428
                                to_wbmux = spr_dat_dmmu;
429
                        `OR1200_SPR_GROUP_IMMU:
430
                                to_wbmux = spr_dat_immu;
431
                        `OR1200_SPR_GROUP_MAC:
432
                                to_wbmux = spr_dat_mac;
433
                        default: //`OR1200_SPR_GROUP_DU:
434
                                to_wbmux = spr_dat_du;
435
                endcase
436 10 unneback
end
437
 
438
endmodule

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