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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's interface to SPRs                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  Decoding of SPR addresses and access to SPRs                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_sprs.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Structure reordered and bugs fixed. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_sprs(
                // Clk & Rst
                clk, rst,
 
                // Internal CPU interface
                flagforw, flag_we, flag, cyforw, cy_we, carry,
                addrbase, addrofs, dat_i, branch_op, ex_spr_read, ex_spr_write,
                epcr, eear, esr, except_started,
                to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
                spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
                boot_adr_sel_i,
 
                // Floating point SPR input
                fpcsr, fpcsr_we, spr_dat_fpu,
 
                // From/to other RISC units
                spr_dat_pic, spr_dat_tt, spr_dat_pm,
                spr_dat_dmmu, spr_dat_immu, spr_dat_du,
                spr_addr, spr_dat_o, spr_cs, spr_we,
 
                du_addr, du_dat_du, du_read,
                du_write, du_dat_cpu
 
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O Ports
//
 
//
// Internal CPU interface
//
input                           clk;            // Clock
input                           rst;            // Reset
input                           flagforw;       // From ALU
input                           flag_we;        // From ALU
output                          flag;           // SR[F]
input                           cyforw;         // From ALU
input                           cy_we;          // From ALU
output                          carry;          // SR[CY]
input   [width-1:0]              addrbase;       // SPR base address
input   [15:0]                   addrofs;        // SPR offset
input   [width-1:0]              dat_i;          // SPR write data
input                           ex_spr_read;    // l.mfspr in EX
input                           ex_spr_write;   // l.mtspr in EX
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch operation
input   [width-1:0]              epcr;           // EPCR0
input   [width-1:0]              eear;           // EEAR0
input   [`OR1200_SR_WIDTH-1:0]   esr;            // ESR0
input                           except_started; // Exception was started
output  [width-1:0]              to_wbmux;       // For l.mfspr
output                          epcr_we;        // EPCR0 write enable
output                          eear_we;        // EEAR0 write enable
output                          esr_we;         // ESR0 write enable
output                          pc_we;          // PC write enable
output                          sr_we;          // Write enable SR
output  [`OR1200_SR_WIDTH-1:0]   to_sr;          // Data to SR
output  [`OR1200_SR_WIDTH-1:0]   sr;             // SR
input   [31:0]                   spr_dat_cfgr;   // Data from CFGR
input   [31:0]                   spr_dat_rf;     // Data from RF
input   [31:0]                   spr_dat_npc;    // Data from NPC
input   [31:0]                   spr_dat_ppc;    // Data from PPC   
input   [31:0]                   spr_dat_mac;    // Data from MAC
input                           boot_adr_sel_i;
 
input   [`OR1200_FPCSR_WIDTH-1:0]       fpcsr;   // FPCSR
output                          fpcsr_we;       // Write enable FPCSR   
input [31:0]                     spr_dat_fpu;    // Data from FPU
 
//
// To/from other RISC units
//
input   [31:0]                   spr_dat_pic;    // Data from PIC
input   [31:0]                   spr_dat_tt;     // Data from TT
input   [31:0]                   spr_dat_pm;     // Data from PM
input   [31:0]                   spr_dat_dmmu;   // Data from DMMU
input   [31:0]                   spr_dat_immu;   // Data from IMMU
input   [31:0]                   spr_dat_du;     // Data from DU
output  [31:0]                   spr_addr;       // SPR Address
output  [31:0]                   spr_dat_o;      // Data to unit
output  [31:0]                   spr_cs;         // Unit select
output                          spr_we;         // SPR write enable
 
//
// To/from Debug Unit
//
input   [width-1:0]              du_addr;        // Address
input   [width-1:0]              du_dat_du;      // Data from DU to SPRS
input                           du_read;        // Read qualifier
input                           du_write;       // Write qualifier
output  [width-1:0]              du_dat_cpu;     // Data from SPRS to DU
 
//
// Internal regs & wires
//
reg     [`OR1200_SR_WIDTH-1:0]   sr_reg;                 // SR
reg                             sr_reg_bit_eph;         // SR_EPH bit
reg                             sr_reg_bit_eph_select;  // SR_EPH select
wire                            sr_reg_bit_eph_muxed;   // SR_EPH muxed bit
reg     [`OR1200_SR_WIDTH-1:0]   sr;                     // SR
reg     [width-1:0]              to_wbmux;       // For l.mfspr
wire                            cfgr_sel;       // Select for cfg regs
wire                            rf_sel;         // Select for RF
wire                            npc_sel;        // Select for NPC
wire                            ppc_sel;        // Select for PPC
wire                            sr_sel;         // Select for SR        
wire                            epcr_sel;       // Select for EPCR0
wire                            eear_sel;       // Select for EEAR0
wire                            esr_sel;        // Select for ESR0
wire                            fpcsr_sel;      // Select for FPCSR   
wire    [31:0]                   sys_data;       // Read data from system SPRs
wire                            du_access;      // Debug unit access
reg     [31:0]                   unqualified_cs; // Unqualified chip selects
   wire                         ex_spr_write; // jb
 
//
// Decide if it is debug unit access
//
assign du_access = du_read | du_write;
 
//
// Generate SPR address from base address and offset
// OR from debug unit address
//
assign spr_addr = du_access ? du_addr : (addrbase | {16'h0000, addrofs});
 
//
// SPR is written by debug unit or by l.mtspr
//
assign spr_dat_o = du_write ? du_dat_du : dat_i;
 
//
// debug unit data input:
//  - read of SPRS by debug unit
//  - write into debug unit SPRs by debug unit itself
//  - write into debug unit SPRs by l.mtspr
//
assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;
 
//
// Write into SPRs when DU or l.mtspr
//
assign spr_we = du_write | ( ex_spr_write & !du_access );
 
 
//
// Qualify chip selects
//
assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & sr[`OR1200_SR_SM])}};
 
//
// Decoding of groups
//
always @(spr_addr)
        case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
                `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
                `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
                `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
                `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
                `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
                `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
                `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
                `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
                `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
                `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
                `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
                `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
        endcase
 
//
// SPRs System Group
//
 
//
// What to write into SR
//
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
                (except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
                (spr_we && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
                sr[`OR1200_SR_FO:`OR1200_SR_OV];
assign to_sr[`OR1200_SR_TED] =
                (except_started) ? 1'b1 :
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
                (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED]:
                sr[`OR1200_SR_TED];
assign to_sr[`OR1200_SR_CY] =
                (except_started) ? sr[`OR1200_SR_CY] :
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
                cy_we ? cyforw :
                (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
                sr[`OR1200_SR_CY];
assign to_sr[`OR1200_SR_F] =
                (except_started) ? sr[`OR1200_SR_F] :
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
                flag_we ? flagforw :
                (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
                sr[`OR1200_SR_F];
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
                (except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00, sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
                (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
                sr[`OR1200_SR_CE:`OR1200_SR_SM];
 
//
// Selects for system SPRs
//
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_FPCSR));
 
 
//
// Write enables for system SPRs
//
assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
assign pc_we = (du_write && (npc_sel | ppc_sel));
assign epcr_we = (spr_we && epcr_sel);
assign eear_we = (spr_we && eear_sel);
assign esr_we = (spr_we && esr_sel);
assign fpcsr_we = (spr_we && fpcsr_sel);
 
//
// Output from system SPRs
//
assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
                  (spr_dat_rf & {32{rf_sel}}) |
                  (spr_dat_npc & {32{npc_sel}}) |
                  (spr_dat_ppc & {32{ppc_sel}}) |
                  ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
                  (epcr & {32{epcr_sel}}) |
                  (eear & {32{eear_sel}}) |
                  ({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} & {32{fpcsr_sel}}) |
                  ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
 
//
// Flag alias
//
assign flag = sr[`OR1200_SR_F];
 
//
// Carry alias
//
assign carry = sr[`OR1200_SR_CY];
 
//
// Supervision register
//
always @(posedge clk or posedge rst)
        if (rst)
                sr_reg <=  {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
        else if (except_started)
                sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
        else if (sr_we)
                sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
 
// EPH part of Supervision register
always @(posedge clk or posedge rst)
        // default value 
        if (rst) begin
                sr_reg_bit_eph <=  `OR1200_SR_EPH_DEF;
                sr_reg_bit_eph_select <=  1'b1; // select async. value due to reset state
        end
        // selected value (different from default) is written into FF after reset state
        else if (sr_reg_bit_eph_select) begin
                sr_reg_bit_eph <=  boot_adr_sel_i;      // dynamic value can only be assigned to FF out of reset! 
                sr_reg_bit_eph_select <=  1'b0; // select FF value 
        end
        else if (sr_we) begin
                sr_reg_bit_eph <=  to_sr[`OR1200_SR_EPH];
        end
 
// select async. value of EPH bit after reset 
assign  sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ? boot_adr_sel_i : sr_reg_bit_eph;
 
// EPH part joined together with rest of Supervision register
always @(sr_reg or sr_reg_bit_eph_muxed)
        sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed, sr_reg[`OR1200_SR_WIDTH-4:0]};
 
//
// MTSPR/MFSPR interface
//
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
         spr_dat_fpu or
        spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
                casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
                        `OR1200_SPR_GROUP_SYS:
                                to_wbmux = sys_data;
                        `OR1200_SPR_GROUP_TT:
                                to_wbmux = spr_dat_tt;
                        `OR1200_SPR_GROUP_PIC:
                                to_wbmux = spr_dat_pic;
                        `OR1200_SPR_GROUP_PM:
                                to_wbmux = spr_dat_pm;
                        `OR1200_SPR_GROUP_DMMU:
                                to_wbmux = spr_dat_dmmu;
                        `OR1200_SPR_GROUP_IMMU:
                                to_wbmux = spr_dat_immu;
                        `OR1200_SPR_GROUP_MAC:
                                to_wbmux = spr_dat_mac;
                        `OR1200_SPR_GROUP_FPU:
                                 to_wbmux = spr_dat_fpu;
                        default: //`OR1200_SPR_GROUP_DU:
                                to_wbmux = spr_dat_du;
                endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's interface to SPRs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6	185	julius	`//// http://www.opencores.org/project,or1k ////`
7	10	unneback	`//// ////`
8			`//// Description ////`
9			`//// Decoding of SPR addresses and access to SPRs ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44	142	marcus.erl	`// $Log: or1200_sprs.v,v $`
45			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
46			`// Major update:`
47			`// Structure reordered and bugs fixed.`
48	10	unneback
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52			`include "or1200_defines.v"
53
54			`module or1200_sprs(`
55			`// Clk & Rst`
56			`clk, rst,`
57
58			`// Internal CPU interface`
59			`flagforw, flag_we, flag, cyforw, cy_we, carry,`
60	142	marcus.erl	`addrbase, addrofs, dat_i, branch_op, ex_spr_read, ex_spr_write,`
61	10	unneback	`epcr, eear, esr, except_started,`
62			`to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,`
63			`spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,`
64	142	marcus.erl	`boot_adr_sel_i,`
65	185	julius
66	258	julius	`// Floating point SPR input`
67	186	julius	`fpcsr, fpcsr_we, spr_dat_fpu,`
68	10	unneback
69			`// From/to other RISC units`
70			`spr_dat_pic, spr_dat_tt, spr_dat_pm,`
71			`spr_dat_dmmu, spr_dat_immu, spr_dat_du,`
72			`spr_addr, spr_dat_o, spr_cs, spr_we,`
73
74			`du_addr, du_dat_du, du_read,`
75			`du_write, du_dat_cpu`
76
77			`);`
78
79			parameter width = `OR1200_OPERAND_WIDTH;
80
81			`//`
82			`// I/O Ports`
83			`//`
84
85			`//`
86			`// Internal CPU interface`
87			`//`
88			`input clk; // Clock`
89			`input rst; // Reset`
90			`input flagforw; // From ALU`
91			`input flag_we; // From ALU`
92			`output flag; // SR[F]`
93			`input cyforw; // From ALU`
94			`input cy_we; // From ALU`
95			`output carry; // SR[CY]`
96			`input [width-1:0] addrbase; // SPR base address`
97			`input [15:0] addrofs; // SPR offset`
98			`input [width-1:0] dat_i; // SPR write data`
99	142	marcus.erl	`input ex_spr_read; // l.mfspr in EX`
100			`input ex_spr_write; // l.mtspr in EX`
101	10	unneback	input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
102			`input [width-1:0] epcr; // EPCR0`
103			`input [width-1:0] eear; // EEAR0`
104			input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
105			`input except_started; // Exception was started`
106			`output [width-1:0] to_wbmux; // For l.mfspr`
107			`output epcr_we; // EPCR0 write enable`
108			`output eear_we; // EEAR0 write enable`
109			`output esr_we; // ESR0 write enable`
110			`output pc_we; // PC write enable`
111			`output sr_we; // Write enable SR`
112			output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
113			output [`OR1200_SR_WIDTH-1:0] sr; // SR
114			`input [31:0] spr_dat_cfgr; // Data from CFGR`
115			`input [31:0] spr_dat_rf; // Data from RF`
116			`input [31:0] spr_dat_npc; // Data from NPC`
117			`input [31:0] spr_dat_ppc; // Data from PPC`
118			`input [31:0] spr_dat_mac; // Data from MAC`
119	142	marcus.erl	`input boot_adr_sel_i;`
120	10	unneback
121	185	julius	input [`OR1200_FPCSR_WIDTH-1:0] fpcsr; // FPCSR
122			`output fpcsr_we; // Write enable FPCSR`
123			`input [31:0] spr_dat_fpu; // Data from FPU`
124
125	10	unneback	`//`
126			`// To/from other RISC units`
127			`//`
128			`input [31:0] spr_dat_pic; // Data from PIC`
129			`input [31:0] spr_dat_tt; // Data from TT`
130			`input [31:0] spr_dat_pm; // Data from PM`
131			`input [31:0] spr_dat_dmmu; // Data from DMMU`
132			`input [31:0] spr_dat_immu; // Data from IMMU`
133			`input [31:0] spr_dat_du; // Data from DU`
134			`output [31:0] spr_addr; // SPR Address`
135			`output [31:0] spr_dat_o; // Data to unit`
136			`output [31:0] spr_cs; // Unit select`
137			`output spr_we; // SPR write enable`
138
139			`//`
140			`// To/from Debug Unit`
141			`//`
142			`input [width-1:0] du_addr; // Address`
143			`input [width-1:0] du_dat_du; // Data from DU to SPRS`
144			`input du_read; // Read qualifier`
145			`input du_write; // Write qualifier`
146			`output [width-1:0] du_dat_cpu; // Data from SPRS to DU`
147
148			`//`
149			`// Internal regs & wires`
150			`//`
151	142	marcus.erl	reg [`OR1200_SR_WIDTH-1:0] sr_reg; // SR
152			`reg sr_reg_bit_eph; // SR_EPH bit`
153			`reg sr_reg_bit_eph_select; // SR_EPH select`
154			`wire sr_reg_bit_eph_muxed; // SR_EPH muxed bit`
155			reg [`OR1200_SR_WIDTH-1:0] sr; // SR
156	10	unneback	`reg [width-1:0] to_wbmux; // For l.mfspr`
157			`wire cfgr_sel; // Select for cfg regs`
158			`wire rf_sel; // Select for RF`
159			`wire npc_sel; // Select for NPC`
160			`wire ppc_sel; // Select for PPC`
161			`wire sr_sel; // Select for SR`
162			`wire epcr_sel; // Select for EPCR0`
163			`wire eear_sel; // Select for EEAR0`
164			`wire esr_sel; // Select for ESR0`
165	185	julius	`wire fpcsr_sel; // Select for FPCSR`
166	10	unneback	`wire [31:0] sys_data; // Read data from system SPRs`
167			`wire du_access; // Debug unit access`
168			`reg [31:0] unqualified_cs; // Unqualified chip selects`
169	142	marcus.erl	`wire ex_spr_write; // jb`
170
171	10	unneback	`//`
172			`// Decide if it is debug unit access`
173			`//`
174			`assign du_access = du_read \| du_write;`
175
176			`//`
177			`// Generate SPR address from base address and offset`
178			`// OR from debug unit address`
179			`//`
180	142	marcus.erl	`assign spr_addr = du_access ? du_addr : (addrbase \| {16'h0000, addrofs});`
181	10	unneback
182			`//`
183			`// SPR is written by debug unit or by l.mtspr`
184			`//`
185			`assign spr_dat_o = du_write ? du_dat_du : dat_i;`
186
187			`//`
188			`// debug unit data input:`
189	142	marcus.erl	`// - read of SPRS by debug unit`
190	10	unneback	`// - write into debug unit SPRs by debug unit itself`
191			`// - write into debug unit SPRs by l.mtspr`
192			`//`
193	142	marcus.erl	`assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;`
194	10	unneback
195			`//`
196	142	marcus.erl	`// Write into SPRs when DU or l.mtspr`
197	10	unneback	`//`
198	151	marcus.erl	`assign spr_we = du_write \| ( ex_spr_write & !du_access );`
199	10	unneback
200	151	marcus.erl
201	10	unneback	`//`
202			`// Qualify chip selects`
203			`//`
204	142	marcus.erl	assign spr_cs = unqualified_cs & {32{du_read \| du_write \| ex_spr_read \| (ex_spr_write & sr[`OR1200_SR_SM])}};
205	10	unneback
206			`//`
207			`// Decoding of groups`
208			`//`
209			`always @(spr_addr)`
210			case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
211			`OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
212			`OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
213			`OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
214			`OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
215			`OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
216			`OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
217			`OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
218			`OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
219			`OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
220			`OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
221			`OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
222			`OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
223			`OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
224			`OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
225			`OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
226			`OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
227			`OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
228			`OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
229			`OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
230			`OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
231			`OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
232			`OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
233			`OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
234			`OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
235			`OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
236			`OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
237			`OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
238			`OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
239			`OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
240			`OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
241			`OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
242			`OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
243			`endcase`
244
245			`//`
246			`// SPRs System Group`
247			`//`
248
249			`//`
250			`// What to write into SR`
251			`//`
252			assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
253	142	marcus.erl	(except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
254	10	unneback	(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
255	142	marcus.erl	(spr_we && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
256	10	unneback	sr[`OR1200_SR_FO:`OR1200_SR_OV];
257	142	marcus.erl	assign to_sr[`OR1200_SR_TED] =
258			`(except_started) ? 1'b1 :`
259			(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
260			(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED]:
261			sr[`OR1200_SR_TED];
262	10	unneback	assign to_sr[`OR1200_SR_CY] =
263	142	marcus.erl	(except_started) ? sr[`OR1200_SR_CY] :
264	10	unneback	(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
265			`cy_we ? cyforw :`
266	142	marcus.erl	(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
267	10	unneback	sr[`OR1200_SR_CY];
268			assign to_sr[`OR1200_SR_F] =
269	142	marcus.erl	(except_started) ? sr[`OR1200_SR_F] :
270	10	unneback	(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
271			`flag_we ? flagforw :`
272	142	marcus.erl	(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
273	10	unneback	sr[`OR1200_SR_F];
274			assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
275	142	marcus.erl	(except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00, sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
276	10	unneback	(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
277	142	marcus.erl	(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
278	10	unneback	sr[`OR1200_SR_CE:`OR1200_SR_SM];
279
280			`//`
281			`// Selects for system SPRs`
282			`//`
283			assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
284			assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
285			assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
286			assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
287			assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
288			assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
289			assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
290			assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
291	185	julius	assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_FPCSR));
292	10	unneback
293	258	julius
294	10	unneback	`//`
295			`// Write enables for system SPRs`
296			`//`
297	142	marcus.erl	assign sr_we = (spr_we && sr_sel) \| (branch_op == `OR1200_BRANCHOP_RFE) \| flag_we \| cy_we;
298			`assign pc_we = (du_write && (npc_sel \| ppc_sel));`
299			`assign epcr_we = (spr_we && epcr_sel);`
300			`assign eear_we = (spr_we && eear_sel);`
301			`assign esr_we = (spr_we && esr_sel);`
302	185	julius	`assign fpcsr_we = (spr_we && fpcsr_sel);`
303	258	julius
304	10	unneback	`//`
305			`// Output from system SPRs`
306			`//`
307	142	marcus.erl	`assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) \|`
308			`(spr_dat_rf & {32{rf_sel}}) \|`
309			`(spr_dat_npc & {32{npc_sel}}) \|`
310			`(spr_dat_ppc & {32{ppc_sel}}) \|`
311			({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) \|
312			`(epcr & {32{epcr_sel}}) \|`
313			`(eear & {32{eear_sel}}) \|`
314	187	julius	({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} & {32{fpcsr_sel}}) \|
315	142	marcus.erl	({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
316	10	unneback
317			`//`
318			`// Flag alias`
319			`//`
320			assign flag = sr[`OR1200_SR_F];
321
322			`//`
323			`// Carry alias`
324			`//`
325			assign carry = sr[`OR1200_SR_CY];
326
327			`//`
328			`// Supervision register`
329			`//`
330			`always @(posedge clk or posedge rst)`
331			`if (rst)`
332	258	julius	sr_reg <= {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
333	142	marcus.erl	`else if (except_started)`
334	258	julius	sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
335	10	unneback	`else if (sr_we)`
336	258	julius	sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
337	10	unneback
338	142	marcus.erl	`// EPH part of Supervision register`
339			`always @(posedge clk or posedge rst)`
340			`// default value`
341			`if (rst) begin`
342	258	julius	sr_reg_bit_eph <= `OR1200_SR_EPH_DEF;
343			`sr_reg_bit_eph_select <= 1'b1; // select async. value due to reset state`
344	142	marcus.erl	`end`
345			`// selected value (different from default) is written into FF after reset state`
346			`else if (sr_reg_bit_eph_select) begin`
347	258	julius	`sr_reg_bit_eph <= boot_adr_sel_i; // dynamic value can only be assigned to FF out of reset!`
348			`sr_reg_bit_eph_select <= 1'b0; // select FF value`
349	142	marcus.erl	`end`
350			`else if (sr_we) begin`
351	258	julius	sr_reg_bit_eph <= to_sr[`OR1200_SR_EPH];
352	142	marcus.erl	`end`
353
354			`// select async. value of EPH bit after reset`
355			`assign sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ? boot_adr_sel_i : sr_reg_bit_eph;`
356
357			`// EPH part joined together with rest of Supervision register`
358			`always @(sr_reg or sr_reg_bit_eph_muxed)`
359			sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed, sr_reg[`OR1200_SR_WIDTH-4:0]};
360
361	10	unneback	`//`
362			`// MTSPR/MFSPR interface`
363			`//`
364	142	marcus.erl	`always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or`
365	185	julius	`spr_dat_fpu or`
366	10	unneback	`spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin`
367	142	marcus.erl	casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
368			`OR1200_SPR_GROUP_SYS:
369			`to_wbmux = sys_data;`
370			`OR1200_SPR_GROUP_TT:
371			`to_wbmux = spr_dat_tt;`
372			`OR1200_SPR_GROUP_PIC:
373			`to_wbmux = spr_dat_pic;`
374			`OR1200_SPR_GROUP_PM:
375			`to_wbmux = spr_dat_pm;`
376			`OR1200_SPR_GROUP_DMMU:
377			`to_wbmux = spr_dat_dmmu;`
378			`OR1200_SPR_GROUP_IMMU:
379			`to_wbmux = spr_dat_immu;`
380			`OR1200_SPR_GROUP_MAC:
381			`to_wbmux = spr_dat_mac;`
382	185	julius	`OR1200_SPR_GROUP_FPU:
383			`to_wbmux = spr_dat_fpu;`
384	142	marcus.erl	default: //`OR1200_SPR_GROUP_DU:
385			`to_wbmux = spr_dat_du;`
386			`endcase`
387	10	unneback	`end`
388
389			`endmodule`

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