OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Blame information for rev 615

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's interface to SPRs                                  ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Decoding of SPR addresses and access to SPRs                ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44 142 marcus.erl
// $Log: or1200_sprs.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Major update: 
47
// Structure reordered and bugs fixed. 
48 10 unneback
 
49
// synopsys translate_off
50
`include "timescale.v"
51
// synopsys translate_on
52
`include "or1200_defines.v"
53
 
54
module or1200_sprs(
55 481 julius
                   // Clk & Rst
56
                   clk, rst,
57 10 unneback
 
58 481 julius
                   // Internal CPU interface
59
                   flagforw, flag_we, flag, cyforw, cy_we, carry,
60
                   addrbase, addrofs, dat_i, branch_op, ex_spr_read,
61
                   ex_spr_write,
62
                   epcr, eear, esr, except_started,
63
                   to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
64
                   spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc,
65
                   spr_dat_mac,
66
 
67
                   boot_adr_sel_i,
68 10 unneback
 
69 481 julius
                   // Floating point SPR input
70
                   fpcsr, fpcsr_we, spr_dat_fpu,
71 10 unneback
 
72 481 julius
                   // From/to other RISC units
73
                   spr_dat_pic, spr_dat_tt, spr_dat_pm,
74
                   spr_dat_dmmu, spr_dat_immu, spr_dat_du,
75
                   spr_addr, spr_dat_o, spr_cs, spr_we,
76 10 unneback
 
77 481 julius
                   du_addr, du_dat_du, du_read,
78
                   du_write, du_dat_cpu
79 10 unneback
 
80 481 julius
                   );
81 10 unneback
 
82 481 julius
   parameter width = `OR1200_OPERAND_WIDTH;
83 10 unneback
 
84 481 julius
   //
85
   // I/O Ports
86
   //
87 10 unneback
 
88 481 julius
   //
89
   // Internal CPU interface
90
   //
91
   input                                clk;            // Clock
92
   input                                rst;            // Reset
93
   input                                flagforw;       // From ALU
94
   input                                flag_we;        // From ALU
95
   output                               flag;           // SR[F]
96
   input                                cyforw;         // From ALU
97
   input                                cy_we;          // From ALU
98
   output                               carry;          // SR[CY]
99
   input [width-1:0]                     addrbase;       // SPR base address
100
   input [15:0]                  addrofs;        // SPR offset
101
   input [width-1:0]                     dat_i;          // SPR write data
102
   input                                ex_spr_read;    // l.mfspr in EX
103
   input                                ex_spr_write;   // l.mtspr in EX
104
   input [`OR1200_BRANCHOP_WIDTH-1:0]    branch_op;      // Branch operation
105
   input [width-1:0]                     epcr /* verilator public */;// EPCR0
106
   input [width-1:0]                     eear /* verilator public */;// EEAR0
107
   input [`OR1200_SR_WIDTH-1:0]  esr /* verilator public */; // ESR0
108
   input                                except_started; // Exception was started
109
   output [width-1:0]                    to_wbmux;       // For l.mfspr
110
   output                               epcr_we;        // EPCR0 write enable
111
   output                               eear_we;        // EEAR0 write enable
112
   output                               esr_we;         // ESR0 write enable
113
   output                               pc_we;          // PC write enable
114
   output                               sr_we;          // Write enable SR
115
   output [`OR1200_SR_WIDTH-1:0]         to_sr;          // Data to SR
116
   output [`OR1200_SR_WIDTH-1:0]         sr /* verilator public */;// SR
117
   input [31:0]                  spr_dat_cfgr;   // Data from CFGR
118
   input [31:0]                  spr_dat_rf;     // Data from RF
119
   input [31:0]                  spr_dat_npc;    // Data from NPC
120
   input [31:0]                  spr_dat_ppc;    // Data from PPC   
121
   input [31:0]                  spr_dat_mac;    // Data from MAC
122
   input                                boot_adr_sel_i;
123
 
124
   input [`OR1200_FPCSR_WIDTH-1:0]       fpcsr;  // FPCSR
125
   output                               fpcsr_we;       // Write enable FPCSR   
126
   input [31:0]                  spr_dat_fpu;    // Data from FPU
127 185 julius
 
128 481 julius
   //
129
   // To/from other RISC units
130
   //
131
   input [31:0]                  spr_dat_pic;    // Data from PIC
132
   input [31:0]                  spr_dat_tt;     // Data from TT
133
   input [31:0]                  spr_dat_pm;     // Data from PM
134
   input [31:0]                  spr_dat_dmmu;   // Data from DMMU
135
   input [31:0]                  spr_dat_immu;   // Data from IMMU
136
   input [31:0]                  spr_dat_du;     // Data from DU
137
   output [31:0]                         spr_addr;       // SPR Address
138
   output [31:0]                         spr_dat_o;      // Data to unit
139
   output [31:0]                         spr_cs;         // Unit select
140
   output                               spr_we;         // SPR write enable
141 10 unneback
 
142 481 julius
   //
143
   // To/from Debug Unit
144
   //
145
   input [width-1:0]                     du_addr;        // Address
146
   input [width-1:0]                     du_dat_du;      // Data from DU to SPRS
147
   input                                du_read;        // Read qualifier
148
   input                                du_write;       // Write qualifier
149
   output [width-1:0]                    du_dat_cpu;     // Data from SPRS to DU
150 10 unneback
 
151 481 julius
   //
152
   // Internal regs & wires
153
   //
154
   reg [`OR1200_SR_WIDTH-1:0]            sr_reg;         // SR
155
   reg                                  sr_reg_bit_eph; // SR_EPH bit
156
   reg                                  sr_reg_bit_eph_select;// SR_EPH select
157
   wire                                 sr_reg_bit_eph_muxed;// SR_EPH muxed bit
158
   reg [`OR1200_SR_WIDTH-1:0]            sr;                     // SR
159
   reg [width-1:0]                       to_wbmux;       // For l.mfspr
160
   wire                                 cfgr_sel;       // Select for cfg regs
161
   wire                                 rf_sel;         // Select for RF
162
   wire                                 npc_sel;        // Select for NPC
163
   wire                                 ppc_sel;        // Select for PPC
164
   wire                                 sr_sel;         // Select for SR        
165
   wire                                 epcr_sel;       // Select for EPCR0
166
   wire                                 eear_sel;       // Select for EEAR0
167
   wire                                 esr_sel;        // Select for ESR0
168
   wire                                 fpcsr_sel;      // Select for FPCSR   
169
   wire [31:0]                           sys_data;// Read data from system SPRs
170
   wire                                 du_access;// Debug unit access
171
   reg [31:0]                            unqualified_cs; // Unqualified selects
172
   wire                                 ex_spr_write; // jb
173 142 marcus.erl
 
174 481 julius
   //
175
   // Decide if it is debug unit access
176
   //
177
   assign du_access = du_read | du_write;
178 10 unneback
 
179 481 julius
   //
180
   // Generate SPR address from base address and offset
181
   // OR from debug unit address
182
   //
183
   assign spr_addr = du_access ? du_addr : (addrbase | {16'h0000, addrofs});
184 10 unneback
 
185 481 julius
   //
186
   // SPR is written by debug unit or by l.mtspr
187
   //
188
   assign spr_dat_o = du_write ? du_dat_du : dat_i;
189 10 unneback
 
190 481 julius
   //
191
   // debug unit data input:
192
   //  - read of SPRS by debug unit
193
   //  - write into debug unit SPRs by debug unit itself
194
   //  - write into debug unit SPRs by l.mtspr
195
   //
196
   assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;
197 10 unneback
 
198 481 julius
   //
199
   // Write into SPRs when DU or l.mtspr
200
   //
201
   assign spr_we = du_write | ( ex_spr_write & !du_access );
202 10 unneback
 
203 151 marcus.erl
 
204 481 julius
   //
205
   // Qualify chip selects
206
   //
207
   assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read |
208
                                        (ex_spr_write & sr[`OR1200_SR_SM])}};
209 10 unneback
 
210 481 julius
   //
211
   // Decoding of groups
212
   //
213
   always @(spr_addr)
214
     case (spr_addr[`OR1200_SPR_GROUP_BITS])    // synopsys parallel_case
215
       `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs
216
         = 32'b00000000_00000000_00000000_00000001;
217
       `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs
218
         = 32'b00000000_00000000_00000000_00000010;
219
       `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs
220
         = 32'b00000000_00000000_00000000_00000100;
221
       `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs
222
         = 32'b00000000_00000000_00000000_00001000;
223
       `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs
224
         = 32'b00000000_00000000_00000000_00010000;
225
       `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs
226
         = 32'b00000000_00000000_00000000_00100000;
227
       `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs
228
         = 32'b00000000_00000000_00000000_01000000;
229
       `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs
230
         = 32'b00000000_00000000_00000000_10000000;
231
       `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs
232
         = 32'b00000000_00000000_00000001_00000000;
233
       `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs
234
         = 32'b00000000_00000000_00000010_00000000;
235
       `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs
236
         = 32'b00000000_00000000_00000100_00000000;
237
       `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs
238
         = 32'b00000000_00000000_00001000_00000000;
239
       `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs
240
         = 32'b00000000_00000000_00010000_00000000;
241
       `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs
242
         = 32'b00000000_00000000_00100000_00000000;
243
       `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs
244
         = 32'b00000000_00000000_01000000_00000000;
245
       `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs
246
         = 32'b00000000_00000000_10000000_00000000;
247
       `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs
248
         = 32'b00000000_00000001_00000000_00000000;
249
       `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs
250
         = 32'b00000000_00000010_00000000_00000000;
251
       `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs
252
         = 32'b00000000_00000100_00000000_00000000;
253
       `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs
254
         = 32'b00000000_00001000_00000000_00000000;
255
       `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs
256
         = 32'b00000000_00010000_00000000_00000000;
257
       `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs
258
         = 32'b00000000_00100000_00000000_00000000;
259
       `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs
260
         = 32'b00000000_01000000_00000000_00000000;
261
       `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs
262
         = 32'b00000000_10000000_00000000_00000000;
263
       `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs
264
         = 32'b00000001_00000000_00000000_00000000;
265
       `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs
266
         = 32'b00000010_00000000_00000000_00000000;
267
       `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs
268
         = 32'b00000100_00000000_00000000_00000000;
269
       `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs
270
         = 32'b00001000_00000000_00000000_00000000;
271
       `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs
272
         = 32'b00010000_00000000_00000000_00000000;
273
       `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs
274
         = 32'b00100000_00000000_00000000_00000000;
275
       `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs
276
         = 32'b01000000_00000000_00000000_00000000;
277
       `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs
278
         = 32'b10000000_00000000_00000000_00000000;
279
     endcase
280 10 unneback
 
281 481 julius
   //
282
   // SPRs System Group
283
   //
284 10 unneback
 
285 481 julius
   //
286
   // What to write into SR
287
   //
288
   assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV]
289
            = (except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
290
              (branch_op == `OR1200_BRANCHOP_RFE) ?
291
              esr[`OR1200_SR_FO:`OR1200_SR_OV] : (spr_we && sr_sel) ?
292
              {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]} :
293
              sr[`OR1200_SR_FO:`OR1200_SR_OV];
294
   assign to_sr[`OR1200_SR_TED]
295
            = (except_started) ? 1'b1 :
296
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
297
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED] :
298
              sr[`OR1200_SR_TED];
299
 
300
   assign to_sr[`OR1200_SR_CY]
301
            = (except_started) ? sr[`OR1200_SR_CY] :
302
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
303
              cy_we ? cyforw :
304
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
305
              sr[`OR1200_SR_CY];
306
   assign to_sr[`OR1200_SR_F]
307
            = (except_started) ? sr[`OR1200_SR_F] :
308
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
309
              flag_we ? flagforw :
310
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
311
              sr[`OR1200_SR_F];
312
 
313
   assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM]
314
            = (except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00,
315
                                  sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
316
              (branch_op == `OR1200_BRANCHOP_RFE) ?
317
              esr[`OR1200_SR_CE:`OR1200_SR_SM] : (spr_we && sr_sel) ?
318
              spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM] :
319
              sr[`OR1200_SR_CE:`OR1200_SR_SM];
320 10 unneback
 
321 481 julius
   //
322
   // Selects for system SPRs
323
   //
324
   assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
325
                      (spr_addr[10:4] == `OR1200_SPR_CFGR));
326
   assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
327
                    (spr_addr[10:5] == `OR1200_SPR_RF));
328
   assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
329
                     (spr_addr[10:0] == `OR1200_SPR_NPC));
330
   assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
331
                     (spr_addr[10:0] == `OR1200_SPR_PPC));
332
   assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
333
                    (spr_addr[10:0] == `OR1200_SPR_SR));
334
   assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
335
                      (spr_addr[10:0] == `OR1200_SPR_EPCR));
336
   assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
337
                      (spr_addr[10:0] == `OR1200_SPR_EEAR));
338
   assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
339
                     (spr_addr[10:0] == `OR1200_SPR_ESR));
340
   assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
341
                       (spr_addr[10:0] == `OR1200_SPR_FPCSR));
342 10 unneback
 
343 258 julius
 
344 481 julius
   //
345
   // Write enables for system SPRs
346
   //
347
   assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) |
348
                  flag_we | cy_we;
349
   assign pc_we = (du_write && (npc_sel | ppc_sel));
350
   assign epcr_we = (spr_we && epcr_sel);
351
   assign eear_we = (spr_we && eear_sel);
352
   assign esr_we = (spr_we && esr_sel);
353
   assign fpcsr_we = (spr_we && fpcsr_sel);
354 258 julius
 
355 481 julius
   //
356
   // Output from system SPRs
357
   //
358
   assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
359
                     (spr_dat_rf & {32{rf_sel}}) |
360
                     (spr_dat_npc & {32{npc_sel}}) |
361
                     (spr_dat_ppc & {32{ppc_sel}}) |
362
                     ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
363
                     (epcr & {32{epcr_sel}}) |
364
                     (eear & {32{eear_sel}}) |
365
                     ({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} &
366
                      {32{fpcsr_sel}}) |
367
                     ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
368 10 unneback
 
369 481 julius
   //
370
   // Flag alias
371
   //
372
   assign flag = sr[`OR1200_SR_F];
373 10 unneback
 
374 481 julius
   //
375
   // Carry alias
376
   //
377
   assign carry = sr[`OR1200_SR_CY];
378 10 unneback
 
379 481 julius
   //
380
   // Supervision register
381
   //
382
   always @(posedge clk or `OR1200_RST_EVENT rst)
383
     if (rst == `OR1200_RST_VALUE)
384
       sr_reg <=  {2'b01, // Fixed one.
385
                   `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
386
     else if (except_started)
387
       sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
388
     else if (sr_we)
389
       sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
390 10 unneback
 
391 481 julius
   // EPH part of Supervision register
392
   always @(posedge clk or `OR1200_RST_EVENT rst)
393
     // default value 
394
     if (rst == `OR1200_RST_VALUE) begin
395
        sr_reg_bit_eph <=  `OR1200_SR_EPH_DEF;
396
        // select async. value due to reset state
397
        sr_reg_bit_eph_select <=  1'b1;
398
     end
399
   // selected value (different from default) is written into FF after reset 
400
   // state
401
     else if (sr_reg_bit_eph_select) begin
402
        // dynamic value can only be assigned to FF out of reset!
403
        sr_reg_bit_eph <=  boot_adr_sel_i;
404
        sr_reg_bit_eph_select <=  1'b0; // select FF value
405
     end
406
     else if (sr_we) begin
407
        sr_reg_bit_eph <=  to_sr[`OR1200_SR_EPH];
408
     end
409 142 marcus.erl
 
410 481 julius
   // select async. value of EPH bit after reset 
411
   assign       sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ?
412
                                       boot_adr_sel_i : sr_reg_bit_eph;
413 142 marcus.erl
 
414 481 julius
   // EPH part joined together with rest of Supervision register
415
   always @(sr_reg or sr_reg_bit_eph_muxed)
416
     sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed,
417
           sr_reg[`OR1200_SR_WIDTH-4:0]};
418 142 marcus.erl
 
419 353 julius
`ifdef verilator
420
   // Function to access various sprs (for Verilator). Have to hide this from
421
   // simulator, since functions with no inputs are not allowed in IEEE
422
   // 1364-2001.
423
 
424
   function [31:0] get_sr;
425
      // verilator public
426 364 julius
      get_sr = {{32-`OR1200_SR_WIDTH{1'b0}},sr};
427 353 julius
   endfunction // get_sr
428
 
429
   function [31:0] get_epcr;
430
      // verilator public
431
      get_epcr = epcr;
432
   endfunction // get_epcr
433
 
434
   function [31:0] get_eear;
435
      // verilator public
436
      get_eear = eear;
437
   endfunction // get_eear
438
 
439
   function [31:0] get_esr;
440
      // verilator public
441 364 julius
      get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
442 353 julius
   endfunction // get_esr
443
 
444
`endif
445
 
446 481 julius
   //
447
   // MTSPR/MFSPR interface
448
   //
449
   always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
450
            spr_dat_fpu or
451
            spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
452
      casez (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
453
        `OR1200_SPR_GROUP_SYS:
454
          to_wbmux = sys_data;
455
        `OR1200_SPR_GROUP_TT:
456
          to_wbmux = spr_dat_tt;
457
        `OR1200_SPR_GROUP_PIC:
458
          to_wbmux = spr_dat_pic;
459
        `OR1200_SPR_GROUP_PM:
460
          to_wbmux = spr_dat_pm;
461
        `OR1200_SPR_GROUP_DMMU:
462
          to_wbmux = spr_dat_dmmu;
463
        `OR1200_SPR_GROUP_IMMU:
464
          to_wbmux = spr_dat_immu;
465
        `OR1200_SPR_GROUP_MAC:
466
          to_wbmux = spr_dat_mac;
467
        `OR1200_SPR_GROUP_FPU:
468
          to_wbmux = spr_dat_fpu;
469
        default: //`OR1200_SPR_GROUP_DU:
470
          to_wbmux = spr_dat_du;
471
      endcase
472
   end
473 10 unneback
 
474
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.