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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Blame information for rev 156

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200 Top Level                                            ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  OR1200 Top Level                                            ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46 142 marcus.erl
// $Log: or1200_top.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// Major update: 
49
// Structure reordered. 
50
//
51
// Revision 1.13  2004/06/08 18:17:36  lampret
52
// Non-functional changes. Coding style fixes.
53
//
54 10 unneback
// Revision 1.12  2004/04/05 08:29:57  lampret
55
// Merged branch_qmem into main tree.
56
//
57
// Revision 1.10.4.9  2004/02/11 01:40:11  lampret
58
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
59
//
60
// Revision 1.10.4.8  2004/01/17 21:14:14  simons
61
// Errors fixed.
62
//
63
// Revision 1.10.4.7  2004/01/17 19:06:38  simons
64
// Error fixed.
65
//
66
// Revision 1.10.4.6  2004/01/17 18:39:48  simons
67
// Error fixed.
68
//
69
// Revision 1.10.4.5  2004/01/15 06:46:38  markom
70
// interface to debug changed; no more opselect; stb-ack protocol
71
//
72
// Revision 1.10.4.4  2003/12/09 11:46:49  simons
73
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
74
//
75
// Revision 1.10.4.3  2003/12/05 00:08:44  lampret
76
// Fixed instantiation name.
77
//
78
// Revision 1.10.4.2  2003/07/11 01:10:35  lampret
79
// Added three missing wire declarations. No functional changes.
80
//
81
// Revision 1.10.4.1  2003/07/08 15:36:37  lampret
82
// Added embedded memory QMEM.
83
//
84
// Revision 1.10  2002/12/08 08:57:56  lampret
85
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
86
//
87
// Revision 1.9  2002/10/17 20:04:41  lampret
88
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
89
//
90
// Revision 1.8  2002/08/18 19:54:22  lampret
91
// Added store buffer.
92
//
93
// Revision 1.7  2002/07/14 22:17:17  lampret
94
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
95
//
96
// Revision 1.6  2002/03/29 15:16:56  lampret
97
// Some of the warnings fixed.
98
//
99
// Revision 1.5  2002/02/11 04:33:17  lampret
100
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
101
//
102
// Revision 1.4  2002/02/01 19:56:55  lampret
103
// Fixed combinational loops.
104
//
105
// Revision 1.3  2002/01/28 01:16:00  lampret
106
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
107
//
108
// Revision 1.2  2002/01/18 07:56:00  lampret
109
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
110
//
111
// Revision 1.1  2002/01/03 08:16:15  lampret
112
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
113
//
114
// Revision 1.13  2001/11/23 08:38:51  lampret
115
// Changed DSR/DRR behavior and exception detection.
116
//
117
// Revision 1.12  2001/11/20 00:57:22  lampret
118
// Fixed width of du_except.
119
//
120
// Revision 1.11  2001/11/18 08:36:28  lampret
121
// For GDB changed single stepping and disabled trap exception.
122
//
123
// Revision 1.10  2001/10/21 17:57:16  lampret
124
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
125
//
126
// Revision 1.9  2001/10/14 13:12:10  lampret
127
// MP3 version.
128
//
129
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
130
// no message
131
//
132
// Revision 1.4  2001/08/13 03:36:20  lampret
133
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
134
//
135
// Revision 1.3  2001/08/09 13:39:33  lampret
136
// Major clean-up.
137
//
138
// Revision 1.2  2001/07/22 03:31:54  lampret
139
// Fixed RAM's oen bug. Cache bypass under development.
140
//
141
// Revision 1.1  2001/07/20 00:46:21  lampret
142
// Development version of RTL. Libraries are missing.
143
//
144
//
145
 
146
// synopsys translate_off
147
`include "timescale.v"
148
// synopsys translate_on
149
`include "or1200_defines.v"
150
 
151
module or1200_top(
152
        // System
153
        clk_i, rst_i, pic_ints_i, clmode_i,
154
 
155
        // Instruction WISHBONE INTERFACE
156
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
157
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
158
`ifdef OR1200_WB_CAB
159
        iwb_cab_o,
160
`endif
161
`ifdef OR1200_WB_B3
162
        iwb_cti_o, iwb_bte_o,
163
`endif
164
        // Data WISHBONE INTERFACE
165
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
166
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
167
`ifdef OR1200_WB_CAB
168
        dwb_cab_o,
169
`endif
170
`ifdef OR1200_WB_B3
171
        dwb_cti_o, dwb_bte_o,
172
`endif
173
 
174
        // External Debug Interface
175
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
176
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
177
 
178
`ifdef OR1200_BIST
179
        // RAM BIST
180
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
181
`endif
182
        // Power Management
183
        pm_cpustall_i,
184
        pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
185
        pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
186
 
187 142 marcus.erl
,sig_tick
188
 
189 10 unneback
);
190
 
191
parameter dw = `OR1200_OPERAND_WIDTH;
192
parameter aw = `OR1200_OPERAND_WIDTH;
193
parameter ppic_ints = `OR1200_PIC_INTS;
194
 
195
//
196
// I/O
197
//
198
 
199
//
200
// System
201
//
202
input                   clk_i;
203
input                   rst_i;
204
input   [1:0]            clmode_i;       // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
205
input   [ppic_ints-1:0]  pic_ints_i;
206
 
207
//
208
// Instruction WISHBONE interface
209
//
210
input                   iwb_clk_i;      // clock input
211
input                   iwb_rst_i;      // reset input
212
input                   iwb_ack_i;      // normal termination
213
input                   iwb_err_i;      // termination w/ error
214
input                   iwb_rty_i;      // termination w/ retry
215
input   [dw-1:0] iwb_dat_i;      // input data bus
216
output                  iwb_cyc_o;      // cycle valid output
217
output  [aw-1:0] iwb_adr_o;      // address bus outputs
218
output                  iwb_stb_o;      // strobe output
219
output                  iwb_we_o;       // indicates write transfer
220
output  [3:0]            iwb_sel_o;      // byte select outputs
221
output  [dw-1:0] iwb_dat_o;      // output data bus
222
`ifdef OR1200_WB_CAB
223
output                  iwb_cab_o;      // indicates consecutive address burst
224
`endif
225
`ifdef OR1200_WB_B3
226
output  [2:0]            iwb_cti_o;      // cycle type identifier
227
output  [1:0]            iwb_bte_o;      // burst type extension
228
`endif
229
 
230
//
231
// Data WISHBONE interface
232
//
233
input                   dwb_clk_i;      // clock input
234
input                   dwb_rst_i;      // reset input
235
input                   dwb_ack_i;      // normal termination
236
input                   dwb_err_i;      // termination w/ error
237
input                   dwb_rty_i;      // termination w/ retry
238
input   [dw-1:0] dwb_dat_i;      // input data bus
239
output                  dwb_cyc_o;      // cycle valid output
240
output  [aw-1:0] dwb_adr_o;      // address bus outputs
241
output                  dwb_stb_o;      // strobe output
242
output                  dwb_we_o;       // indicates write transfer
243
output  [3:0]            dwb_sel_o;      // byte select outputs
244
output  [dw-1:0] dwb_dat_o;      // output data bus
245
`ifdef OR1200_WB_CAB
246
output                  dwb_cab_o;      // indicates consecutive address burst
247
`endif
248
`ifdef OR1200_WB_B3
249
output  [2:0]            dwb_cti_o;      // cycle type identifier
250
output  [1:0]            dwb_bte_o;      // burst type extension
251
`endif
252
 
253
//
254
// External Debug Interface
255
//
256
input                   dbg_stall_i;    // External Stall Input
257
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
258
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
259
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
260
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
261
output                  dbg_bp_o;       // Breakpoint Output
262
input                   dbg_stb_i;      // External Address/Data Strobe
263
input                   dbg_we_i;       // External Write Enable
264
input   [aw-1:0] dbg_adr_i;      // External Address Input
265
input   [dw-1:0] dbg_dat_i;      // External Data Input
266
output  [dw-1:0] dbg_dat_o;      // External Data Output
267
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
268
 
269
`ifdef OR1200_BIST
270
//
271
// RAM BIST
272
//
273
input mbist_si_i;
274
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
275
output mbist_so_o;
276
`endif
277
 
278
//
279
// Power Management
280
//
281
input                   pm_cpustall_i;
282
output  [3:0]            pm_clksd_o;
283
output                  pm_dc_gate_o;
284
output                  pm_ic_gate_o;
285
output                  pm_dmmu_gate_o;
286
output                  pm_immu_gate_o;
287
output                  pm_tt_gate_o;
288
output                  pm_cpu_gate_o;
289
output                  pm_wakeup_o;
290
output                  pm_lvolt_o;
291
 
292
 
293
//
294
// Internal wires and regs
295
//
296
 
297
//
298
// DC to SB
299
//
300
wire    [dw-1:0] dcsb_dat_dc;
301
wire    [aw-1:0] dcsb_adr_dc;
302
wire                    dcsb_cyc_dc;
303
wire                    dcsb_stb_dc;
304
wire                    dcsb_we_dc;
305
wire    [3:0]            dcsb_sel_dc;
306
wire                    dcsb_cab_dc;
307
wire    [dw-1:0] dcsb_dat_sb;
308
wire                    dcsb_ack_sb;
309
wire                    dcsb_err_sb;
310
 
311
//
312
// SB to BIU
313
//
314
wire    [dw-1:0] sbbiu_dat_sb;
315
wire    [aw-1:0] sbbiu_adr_sb;
316
wire                    sbbiu_cyc_sb;
317
wire                    sbbiu_stb_sb;
318
wire                    sbbiu_we_sb;
319
wire    [3:0]            sbbiu_sel_sb;
320
wire                    sbbiu_cab_sb;
321
wire    [dw-1:0] sbbiu_dat_biu;
322
wire                    sbbiu_ack_biu;
323
wire                    sbbiu_err_biu;
324
 
325
//
326
// IC to BIU
327
//
328
wire    [dw-1:0] icbiu_dat_ic;
329
wire    [aw-1:0] icbiu_adr_ic;
330 142 marcus.erl
wire    [aw-1:0] icbiu_adr_ic_word;
331 10 unneback
wire                    icbiu_cyc_ic;
332
wire                    icbiu_stb_ic;
333
wire                    icbiu_we_ic;
334
wire    [3:0]            icbiu_sel_ic;
335
wire    [3:0]            icbiu_tag_ic;
336
wire                    icbiu_cab_ic;
337
wire    [dw-1:0] icbiu_dat_biu;
338
wire                    icbiu_ack_biu;
339
wire                    icbiu_err_biu;
340
wire    [3:0]            icbiu_tag_biu;
341
 
342
//
343 142 marcus.erl
// SR Interface (this signal can be connected to the input pin)
344
//
345
wire                    boot_adr_sel = `OR1200_SR_EPH_DEF;
346
 
347
//
348 10 unneback
// CPU's SPR access to various RISC units (shared wires)
349
//
350
wire                    supv;
351
wire    [aw-1:0] spr_addr;
352
wire    [dw-1:0] spr_dat_cpu;
353
wire    [31:0]           spr_cs;
354
wire                    spr_we;
355
 
356
//
357 142 marcus.erl
// SB
358
//
359
wire                    sb_en;
360
 
361
//
362 10 unneback
// DMMU and CPU
363
//
364
wire                    dmmu_en;
365
wire    [31:0]           spr_dat_dmmu;
366
 
367
//
368
// DMMU and QMEM
369
//
370
wire                    qmemdmmu_err_qmem;
371
wire    [3:0]            qmemdmmu_tag_qmem;
372
wire    [aw-1:0] qmemdmmu_adr_dmmu;
373
wire                    qmemdmmu_cycstb_dmmu;
374
wire                    qmemdmmu_ci_dmmu;
375
 
376
//
377
// CPU and data memory subsystem
378
//
379
wire                    dc_en;
380
wire    [31:0]           dcpu_adr_cpu;
381
wire                    dcpu_cycstb_cpu;
382
wire                    dcpu_we_cpu;
383
wire    [3:0]            dcpu_sel_cpu;
384
wire    [3:0]            dcpu_tag_cpu;
385
wire    [31:0]           dcpu_dat_cpu;
386
wire    [31:0]           dcpu_dat_qmem;
387
wire                    dcpu_ack_qmem;
388
wire                    dcpu_rty_qmem;
389
wire                    dcpu_err_dmmu;
390
wire    [3:0]            dcpu_tag_dmmu;
391
 
392
//
393
// IMMU and CPU
394
//
395
wire                    immu_en;
396
wire    [31:0]           spr_dat_immu;
397
 
398
//
399
// CPU and insn memory subsystem
400
//
401
wire                    ic_en;
402
wire    [31:0]           icpu_adr_cpu;
403
wire                    icpu_cycstb_cpu;
404
wire    [3:0]            icpu_sel_cpu;
405
wire    [3:0]            icpu_tag_cpu;
406
wire    [31:0]           icpu_dat_qmem;
407
wire                    icpu_ack_qmem;
408
wire    [31:0]           icpu_adr_immu;
409
wire                    icpu_err_immu;
410
wire    [3:0]            icpu_tag_immu;
411
wire                    icpu_rty_immu;
412
 
413
//
414
// IMMU and QMEM
415
//
416
wire    [aw-1:0] qmemimmu_adr_immu;
417
wire                    qmemimmu_rty_qmem;
418
wire                    qmemimmu_err_qmem;
419
wire    [3:0]            qmemimmu_tag_qmem;
420
wire                    qmemimmu_cycstb_immu;
421
wire                    qmemimmu_ci_immu;
422
 
423
//
424
// QMEM and IC
425
//
426
wire    [aw-1:0] icqmem_adr_qmem;
427
wire                    icqmem_rty_ic;
428
wire                    icqmem_err_ic;
429
wire    [3:0]            icqmem_tag_ic;
430
wire                    icqmem_cycstb_qmem;
431
wire                    icqmem_ci_qmem;
432
wire    [31:0]           icqmem_dat_ic;
433
wire                    icqmem_ack_ic;
434
 
435
//
436
// QMEM and DC
437
//
438
wire    [aw-1:0] dcqmem_adr_qmem;
439
wire                    dcqmem_rty_dc;
440
wire                    dcqmem_err_dc;
441
wire    [3:0]            dcqmem_tag_dc;
442
wire                    dcqmem_cycstb_qmem;
443
wire                    dcqmem_ci_qmem;
444
wire    [31:0]           dcqmem_dat_dc;
445
wire    [31:0]           dcqmem_dat_qmem;
446
wire                    dcqmem_we_qmem;
447
wire    [3:0]            dcqmem_sel_qmem;
448
wire                    dcqmem_ack_dc;
449
 
450
//
451
// Connection between CPU and PIC
452
//
453
wire    [dw-1:0] spr_dat_pic;
454
wire                    pic_wakeup;
455
wire                    sig_int;
456
 
457
//
458
// Connection between CPU and PM
459
//
460
wire    [dw-1:0] spr_dat_pm;
461
 
462
//
463
// CPU and TT
464
//
465
wire    [dw-1:0] spr_dat_tt;
466 142 marcus.erl
output wire                     sig_tick; // jb
467 10 unneback
 
468
//
469
// Debug port and caches/MMUs
470
//
471
wire    [dw-1:0] spr_dat_du;
472
wire                    du_stall;
473
wire    [dw-1:0] du_addr;
474
wire    [dw-1:0] du_dat_du;
475
wire                    du_read;
476
wire                    du_write;
477 142 marcus.erl
wire    [12:0]           du_except_trig;
478
wire    [12:0]           du_except_stop;
479 10 unneback
wire    [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
480 142 marcus.erl
wire    [24:0]           du_dmr1;
481 10 unneback
wire    [dw-1:0] du_dat_cpu;
482 142 marcus.erl
wire    [dw-1:0] du_lsu_store_dat;
483
wire    [dw-1:0] du_lsu_load_dat;
484 10 unneback
wire                    du_hwbkpt;
485 142 marcus.erl
wire                    du_hwbkpt_ls_r = 1'b0;
486
wire                    flushpipe;
487 10 unneback
wire                    ex_freeze;
488 142 marcus.erl
wire                    wb_freeze;
489
wire                    id_void;
490
wire                    ex_void;
491
wire    [31:0]           id_insn;
492 10 unneback
wire    [31:0]           ex_insn;
493 142 marcus.erl
wire    [31:0]           wb_insn;
494 10 unneback
wire    [31:0]           id_pc;
495 142 marcus.erl
wire    [31:0]           ex_pc;
496
wire    [31:0]           wb_pc;
497 10 unneback
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
498
wire    [31:0]           spr_dat_npc;
499
wire    [31:0]           rf_dataw;
500 142 marcus.erl
wire                    abort_ex;
501
wire                    abort_mvspr;
502 10 unneback
 
503
`ifdef OR1200_BIST
504
//
505
// RAM BIST
506
//
507
wire                    mbist_immu_so;
508
wire                    mbist_ic_so;
509
wire                    mbist_dmmu_so;
510
wire                    mbist_dc_so;
511 142 marcus.erl
wire                    mbist_qmem_so;
512 10 unneback
wire                    mbist_immu_si = mbist_si_i;
513
wire                    mbist_ic_si = mbist_immu_so;
514
wire                    mbist_qmem_si = mbist_ic_so;
515
wire                    mbist_dmmu_si = mbist_qmem_so;
516
wire                    mbist_dc_si = mbist_dmmu_so;
517
assign                  mbist_so_o = mbist_dc_so;
518
`endif
519
 
520
wire  [3:0] icqmem_sel_qmem;
521
wire  [3:0] icqmem_tag_qmem;
522
wire  [3:0] dcqmem_tag_qmem;
523
 
524
//
525
// Instantiation of Instruction WISHBONE BIU
526
//
527 142 marcus.erl
or1200_wb_biu iwb_biu(
528 10 unneback
        // RISC clk, rst and clock control
529
        .clk(clk_i),
530
        .rst(rst_i),
531
        .clmode(clmode_i),
532
 
533
        // WISHBONE interface
534
        .wb_clk_i(iwb_clk_i),
535
        .wb_rst_i(iwb_rst_i),
536
        .wb_ack_i(iwb_ack_i),
537
        .wb_err_i(iwb_err_i),
538
        .wb_rty_i(iwb_rty_i),
539
        .wb_dat_i(iwb_dat_i),
540
        .wb_cyc_o(iwb_cyc_o),
541
        .wb_adr_o(iwb_adr_o),
542
        .wb_stb_o(iwb_stb_o),
543
        .wb_we_o(iwb_we_o),
544
        .wb_sel_o(iwb_sel_o),
545
        .wb_dat_o(iwb_dat_o),
546
`ifdef OR1200_WB_CAB
547
        .wb_cab_o(iwb_cab_o),
548
`endif
549
`ifdef OR1200_WB_B3
550
        .wb_cti_o(iwb_cti_o),
551
        .wb_bte_o(iwb_bte_o),
552
`endif
553
 
554
        // Internal RISC bus
555
        .biu_dat_i(icbiu_dat_ic),
556 142 marcus.erl
        .biu_adr_i(icbiu_adr_ic_word),
557 10 unneback
        .biu_cyc_i(icbiu_cyc_ic),
558
        .biu_stb_i(icbiu_stb_ic),
559
        .biu_we_i(icbiu_we_ic),
560
        .biu_sel_i(icbiu_sel_ic),
561
        .biu_cab_i(icbiu_cab_ic),
562
        .biu_dat_o(icbiu_dat_biu),
563
        .biu_ack_o(icbiu_ack_biu),
564
        .biu_err_o(icbiu_err_biu)
565
);
566 142 marcus.erl
assign icbiu_adr_ic_word = {icbiu_adr_ic[31:2], 2'h0};
567 10 unneback
 
568
//
569
// Instantiation of Data WISHBONE BIU
570
//
571
or1200_wb_biu dwb_biu(
572
        // RISC clk, rst and clock control
573
        .clk(clk_i),
574
        .rst(rst_i),
575
        .clmode(clmode_i),
576
 
577
        // WISHBONE interface
578
        .wb_clk_i(dwb_clk_i),
579
        .wb_rst_i(dwb_rst_i),
580
        .wb_ack_i(dwb_ack_i),
581
        .wb_err_i(dwb_err_i),
582
        .wb_rty_i(dwb_rty_i),
583
        .wb_dat_i(dwb_dat_i),
584
        .wb_cyc_o(dwb_cyc_o),
585
        .wb_adr_o(dwb_adr_o),
586
        .wb_stb_o(dwb_stb_o),
587
        .wb_we_o(dwb_we_o),
588
        .wb_sel_o(dwb_sel_o),
589
        .wb_dat_o(dwb_dat_o),
590
`ifdef OR1200_WB_CAB
591
        .wb_cab_o(dwb_cab_o),
592
`endif
593
`ifdef OR1200_WB_B3
594
        .wb_cti_o(dwb_cti_o),
595
        .wb_bte_o(dwb_bte_o),
596
`endif
597
 
598
        // Internal RISC bus
599
        .biu_dat_i(sbbiu_dat_sb),
600
        .biu_adr_i(sbbiu_adr_sb),
601
        .biu_cyc_i(sbbiu_cyc_sb),
602
        .biu_stb_i(sbbiu_stb_sb),
603
        .biu_we_i(sbbiu_we_sb),
604
        .biu_sel_i(sbbiu_sel_sb),
605
        .biu_cab_i(sbbiu_cab_sb),
606
        .biu_dat_o(sbbiu_dat_biu),
607
        .biu_ack_o(sbbiu_ack_biu),
608
        .biu_err_o(sbbiu_err_biu)
609
);
610
 
611
//
612
// Instantiation of IMMU
613
//
614
or1200_immu_top or1200_immu_top(
615
        // Rst and clk
616
        .clk(clk_i),
617
        .rst(rst_i),
618
 
619
`ifdef OR1200_BIST
620
        // RAM BIST
621
        .mbist_si_i(mbist_immu_si),
622
        .mbist_so_o(mbist_immu_so),
623
        .mbist_ctrl_i(mbist_ctrl_i),
624
`endif
625
 
626
        // CPU and IMMU
627
        .ic_en(ic_en),
628
        .immu_en(immu_en),
629
        .supv(supv),
630
        .icpu_adr_i(icpu_adr_cpu),
631
        .icpu_cycstb_i(icpu_cycstb_cpu),
632
        .icpu_adr_o(icpu_adr_immu),
633
        .icpu_tag_o(icpu_tag_immu),
634
        .icpu_rty_o(icpu_rty_immu),
635
        .icpu_err_o(icpu_err_immu),
636
 
637 142 marcus.erl
        // SR Interface
638
        .boot_adr_sel_i(boot_adr_sel),
639
 
640 10 unneback
        // SPR access
641
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
642
        .spr_write(spr_we),
643
        .spr_addr(spr_addr),
644
        .spr_dat_i(spr_dat_cpu),
645
        .spr_dat_o(spr_dat_immu),
646
 
647
        // QMEM and IMMU
648
        .qmemimmu_rty_i(qmemimmu_rty_qmem),
649
        .qmemimmu_err_i(qmemimmu_err_qmem),
650
        .qmemimmu_tag_i(qmemimmu_tag_qmem),
651
        .qmemimmu_adr_o(qmemimmu_adr_immu),
652
        .qmemimmu_cycstb_o(qmemimmu_cycstb_immu),
653
        .qmemimmu_ci_o(qmemimmu_ci_immu)
654
);
655
 
656
//
657
// Instantiation of Instruction Cache
658
//
659
or1200_ic_top or1200_ic_top(
660
        .clk(clk_i),
661
        .rst(rst_i),
662
 
663
`ifdef OR1200_BIST
664
        // RAM BIST
665
        .mbist_si_i(mbist_ic_si),
666
        .mbist_so_o(mbist_ic_so),
667
        .mbist_ctrl_i(mbist_ctrl_i),
668
`endif
669
 
670
        // IC and QMEM
671
        .ic_en(ic_en),
672
        .icqmem_adr_i(icqmem_adr_qmem),
673
        .icqmem_cycstb_i(icqmem_cycstb_qmem),
674
        .icqmem_ci_i(icqmem_ci_qmem),
675
        .icqmem_sel_i(icqmem_sel_qmem),
676
        .icqmem_tag_i(icqmem_tag_qmem),
677
        .icqmem_dat_o(icqmem_dat_ic),
678
        .icqmem_ack_o(icqmem_ack_ic),
679
        .icqmem_rty_o(icqmem_rty_ic),
680
        .icqmem_err_o(icqmem_err_ic),
681
        .icqmem_tag_o(icqmem_tag_ic),
682
 
683
        // SPR access
684
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
685
        .spr_write(spr_we),
686
        .spr_dat_i(spr_dat_cpu),
687
 
688
        // IC and BIU
689
        .icbiu_dat_o(icbiu_dat_ic),
690
        .icbiu_adr_o(icbiu_adr_ic),
691
        .icbiu_cyc_o(icbiu_cyc_ic),
692
        .icbiu_stb_o(icbiu_stb_ic),
693
        .icbiu_we_o(icbiu_we_ic),
694
        .icbiu_sel_o(icbiu_sel_ic),
695
        .icbiu_cab_o(icbiu_cab_ic),
696
        .icbiu_dat_i(icbiu_dat_biu),
697
        .icbiu_ack_i(icbiu_ack_biu),
698
        .icbiu_err_i(icbiu_err_biu)
699
);
700
 
701
//
702
// Instantiation of Instruction Cache
703
//
704
or1200_cpu or1200_cpu(
705
        .clk(clk_i),
706
        .rst(rst_i),
707
 
708
        // Connection QMEM and IFETCHER inside CPU
709
        .ic_en(ic_en),
710
        .icpu_adr_o(icpu_adr_cpu),
711
        .icpu_cycstb_o(icpu_cycstb_cpu),
712
        .icpu_sel_o(icpu_sel_cpu),
713
        .icpu_tag_o(icpu_tag_cpu),
714
        .icpu_dat_i(icpu_dat_qmem),
715
        .icpu_ack_i(icpu_ack_qmem),
716
        .icpu_rty_i(icpu_rty_immu),
717
        .icpu_adr_i(icpu_adr_immu),
718
        .icpu_err_i(icpu_err_immu),
719
        .icpu_tag_i(icpu_tag_immu),
720
 
721
        // Connection CPU to external Debug port
722 142 marcus.erl
        .id_void(id_void),
723
        .id_insn(id_insn),
724
        .ex_void(ex_void),
725
        .ex_insn(ex_insn),
726 10 unneback
        .ex_freeze(ex_freeze),
727 142 marcus.erl
        .wb_insn(wb_insn),
728
        .wb_freeze(wb_freeze),
729 10 unneback
        .id_pc(id_pc),
730 142 marcus.erl
        .ex_pc(ex_pc),
731
        .wb_pc(wb_pc),
732 10 unneback
        .branch_op(branch_op),
733 142 marcus.erl
        .rf_dataw(rf_dataw),
734
        .ex_flushpipe(flushpipe),
735 10 unneback
        .du_stall(du_stall),
736
        .du_addr(du_addr),
737
        .du_dat_du(du_dat_du),
738
        .du_read(du_read),
739
        .du_write(du_write),
740 142 marcus.erl
        .du_except_trig(du_except_trig),
741
        .du_except_stop(du_except_stop),
742 10 unneback
        .du_dsr(du_dsr),
743 142 marcus.erl
        .du_dmr1(du_dmr1),
744
        .du_hwbkpt(du_hwbkpt),
745
        .du_hwbkpt_ls_r(du_hwbkpt_ls_r),
746 10 unneback
        .du_dat_cpu(du_dat_cpu),
747 142 marcus.erl
        .du_lsu_store_dat(du_lsu_store_dat),
748
        .du_lsu_load_dat(du_lsu_load_dat),
749
        .abort_mvspr(abort_mvspr),
750
        .abort_ex(abort_ex),
751 10 unneback
 
752
        // Connection IMMU and CPU internally
753
        .immu_en(immu_en),
754
 
755
        // Connection QMEM and CPU
756
        .dc_en(dc_en),
757
        .dcpu_adr_o(dcpu_adr_cpu),
758
        .dcpu_cycstb_o(dcpu_cycstb_cpu),
759
        .dcpu_we_o(dcpu_we_cpu),
760
        .dcpu_sel_o(dcpu_sel_cpu),
761
        .dcpu_tag_o(dcpu_tag_cpu),
762
        .dcpu_dat_o(dcpu_dat_cpu),
763
        .dcpu_dat_i(dcpu_dat_qmem),
764
        .dcpu_ack_i(dcpu_ack_qmem),
765
        .dcpu_rty_i(dcpu_rty_qmem),
766
        .dcpu_err_i(dcpu_err_dmmu),
767
        .dcpu_tag_i(dcpu_tag_dmmu),
768
 
769
        // Connection DMMU and CPU internally
770
        .dmmu_en(dmmu_en),
771
 
772 142 marcus.erl
        // SR Interface
773
        .boot_adr_sel_i(boot_adr_sel),
774
 
775
        // SB Enable
776
        .sb_en(sb_en),
777
 
778 10 unneback
        // Connection PIC and CPU's EXCEPT
779
        .sig_int(sig_int),
780
        .sig_tick(sig_tick),
781
 
782
        // SPRs
783
        .supv(supv),
784
        .spr_addr(spr_addr),
785
        .spr_dat_cpu(spr_dat_cpu),
786
        .spr_dat_pic(spr_dat_pic),
787
        .spr_dat_tt(spr_dat_tt),
788
        .spr_dat_pm(spr_dat_pm),
789
        .spr_dat_dmmu(spr_dat_dmmu),
790
        .spr_dat_immu(spr_dat_immu),
791
        .spr_dat_du(spr_dat_du),
792
        .spr_dat_npc(spr_dat_npc),
793
        .spr_cs(spr_cs),
794
        .spr_we(spr_we)
795
);
796
 
797
//
798
// Instantiation of DMMU
799
//
800
or1200_dmmu_top or1200_dmmu_top(
801
        // Rst and clk
802
        .clk(clk_i),
803
        .rst(rst_i),
804
 
805
`ifdef OR1200_BIST
806
        // RAM BIST
807
        .mbist_si_i(mbist_dmmu_si),
808
        .mbist_so_o(mbist_dmmu_so),
809
        .mbist_ctrl_i(mbist_ctrl_i),
810
`endif
811
 
812
        // CPU i/f
813
        .dc_en(dc_en),
814
        .dmmu_en(dmmu_en),
815
        .supv(supv),
816
        .dcpu_adr_i(dcpu_adr_cpu),
817
        .dcpu_cycstb_i(dcpu_cycstb_cpu),
818
        .dcpu_we_i(dcpu_we_cpu),
819
        .dcpu_tag_o(dcpu_tag_dmmu),
820
        .dcpu_err_o(dcpu_err_dmmu),
821
 
822
        // SPR access
823
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DMMU]),
824
        .spr_write(spr_we),
825
        .spr_addr(spr_addr),
826
        .spr_dat_i(spr_dat_cpu),
827
        .spr_dat_o(spr_dat_dmmu),
828
 
829
        // QMEM and DMMU
830
        .qmemdmmu_err_i(qmemdmmu_err_qmem),
831
        .qmemdmmu_tag_i(qmemdmmu_tag_qmem),
832
        .qmemdmmu_adr_o(qmemdmmu_adr_dmmu),
833
        .qmemdmmu_cycstb_o(qmemdmmu_cycstb_dmmu),
834
        .qmemdmmu_ci_o(qmemdmmu_ci_dmmu)
835
);
836
 
837
//
838
// Instantiation of Data Cache
839
//
840
or1200_dc_top or1200_dc_top(
841
        .clk(clk_i),
842
        .rst(rst_i),
843
 
844
`ifdef OR1200_BIST
845
        // RAM BIST
846
        .mbist_si_i(mbist_dc_si),
847
        .mbist_so_o(mbist_dc_so),
848
        .mbist_ctrl_i(mbist_ctrl_i),
849
`endif
850
 
851
        // DC and QMEM
852
        .dc_en(dc_en),
853
        .dcqmem_adr_i(dcqmem_adr_qmem),
854
        .dcqmem_cycstb_i(dcqmem_cycstb_qmem),
855
        .dcqmem_ci_i(dcqmem_ci_qmem),
856
        .dcqmem_we_i(dcqmem_we_qmem),
857
        .dcqmem_sel_i(dcqmem_sel_qmem),
858
        .dcqmem_tag_i(dcqmem_tag_qmem),
859
        .dcqmem_dat_i(dcqmem_dat_qmem),
860
        .dcqmem_dat_o(dcqmem_dat_dc),
861
        .dcqmem_ack_o(dcqmem_ack_dc),
862
        .dcqmem_rty_o(dcqmem_rty_dc),
863
        .dcqmem_err_o(dcqmem_err_dc),
864
        .dcqmem_tag_o(dcqmem_tag_dc),
865
 
866
        // SPR access
867
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
868
        .spr_write(spr_we),
869
        .spr_dat_i(spr_dat_cpu),
870
 
871
        // DC and BIU
872
        .dcsb_dat_o(dcsb_dat_dc),
873
        .dcsb_adr_o(dcsb_adr_dc),
874
        .dcsb_cyc_o(dcsb_cyc_dc),
875
        .dcsb_stb_o(dcsb_stb_dc),
876
        .dcsb_we_o(dcsb_we_dc),
877
        .dcsb_sel_o(dcsb_sel_dc),
878
        .dcsb_cab_o(dcsb_cab_dc),
879
        .dcsb_dat_i(dcsb_dat_sb),
880
        .dcsb_ack_i(dcsb_ack_sb),
881
        .dcsb_err_i(dcsb_err_sb)
882
);
883
 
884
//
885
// Instantiation of embedded memory - qmem
886
//
887
or1200_qmem_top or1200_qmem_top(
888
        .clk(clk_i),
889
        .rst(rst_i),
890
 
891
`ifdef OR1200_BIST
892
        // RAM BIST
893
        .mbist_si_i(mbist_qmem_si),
894
        .mbist_so_o(mbist_qmem_so),
895
        .mbist_ctrl_i(mbist_ctrl_i),
896
`endif
897
 
898
        // QMEM and CPU/IMMU
899
        .qmemimmu_adr_i(qmemimmu_adr_immu),
900
        .qmemimmu_cycstb_i(qmemimmu_cycstb_immu),
901
        .qmemimmu_ci_i(qmemimmu_ci_immu),
902
        .qmemicpu_sel_i(icpu_sel_cpu),
903
        .qmemicpu_tag_i(icpu_tag_cpu),
904
        .qmemicpu_dat_o(icpu_dat_qmem),
905
        .qmemicpu_ack_o(icpu_ack_qmem),
906
        .qmemimmu_rty_o(qmemimmu_rty_qmem),
907
        .qmemimmu_err_o(qmemimmu_err_qmem),
908
        .qmemimmu_tag_o(qmemimmu_tag_qmem),
909
 
910
        // QMEM and IC
911
        .icqmem_adr_o(icqmem_adr_qmem),
912
        .icqmem_cycstb_o(icqmem_cycstb_qmem),
913
        .icqmem_ci_o(icqmem_ci_qmem),
914
        .icqmem_sel_o(icqmem_sel_qmem),
915
        .icqmem_tag_o(icqmem_tag_qmem),
916
        .icqmem_dat_i(icqmem_dat_ic),
917
        .icqmem_ack_i(icqmem_ack_ic),
918
        .icqmem_rty_i(icqmem_rty_ic),
919
        .icqmem_err_i(icqmem_err_ic),
920
        .icqmem_tag_i(icqmem_tag_ic),
921
 
922
        // QMEM and CPU/DMMU
923
        .qmemdmmu_adr_i(qmemdmmu_adr_dmmu),
924
        .qmemdmmu_cycstb_i(qmemdmmu_cycstb_dmmu),
925
        .qmemdmmu_ci_i(qmemdmmu_ci_dmmu),
926
        .qmemdcpu_we_i(dcpu_we_cpu),
927
        .qmemdcpu_sel_i(dcpu_sel_cpu),
928
        .qmemdcpu_tag_i(dcpu_tag_cpu),
929
        .qmemdcpu_dat_i(dcpu_dat_cpu),
930
        .qmemdcpu_dat_o(dcpu_dat_qmem),
931
        .qmemdcpu_ack_o(dcpu_ack_qmem),
932
        .qmemdcpu_rty_o(dcpu_rty_qmem),
933
        .qmemdmmu_err_o(qmemdmmu_err_qmem),
934
        .qmemdmmu_tag_o(qmemdmmu_tag_qmem),
935
 
936
        // QMEM and DC
937
        .dcqmem_adr_o(dcqmem_adr_qmem),
938
        .dcqmem_cycstb_o(dcqmem_cycstb_qmem),
939
        .dcqmem_ci_o(dcqmem_ci_qmem),
940
        .dcqmem_we_o(dcqmem_we_qmem),
941
        .dcqmem_sel_o(dcqmem_sel_qmem),
942
        .dcqmem_tag_o(dcqmem_tag_qmem),
943
        .dcqmem_dat_o(dcqmem_dat_qmem),
944
        .dcqmem_dat_i(dcqmem_dat_dc),
945
        .dcqmem_ack_i(dcqmem_ack_dc),
946
        .dcqmem_rty_i(dcqmem_rty_dc),
947
        .dcqmem_err_i(dcqmem_err_dc),
948
        .dcqmem_tag_i(dcqmem_tag_dc)
949
);
950
 
951
//
952
// Instantiation of Store Buffer
953
//
954
or1200_sb or1200_sb(
955
        // RISC clock, reset
956
        .clk(clk_i),
957
        .rst(rst_i),
958
 
959 142 marcus.erl
        // Internal RISC bus (SB)
960
        .sb_en(sb_en),
961
 
962 10 unneback
        // Internal RISC bus (DC<->SB)
963
        .dcsb_dat_i(dcsb_dat_dc),
964
        .dcsb_adr_i(dcsb_adr_dc),
965
        .dcsb_cyc_i(dcsb_cyc_dc),
966
        .dcsb_stb_i(dcsb_stb_dc),
967
        .dcsb_we_i(dcsb_we_dc),
968
        .dcsb_sel_i(dcsb_sel_dc),
969
        .dcsb_cab_i(dcsb_cab_dc),
970
        .dcsb_dat_o(dcsb_dat_sb),
971
        .dcsb_ack_o(dcsb_ack_sb),
972
        .dcsb_err_o(dcsb_err_sb),
973
 
974
        // SB and BIU
975
        .sbbiu_dat_o(sbbiu_dat_sb),
976
        .sbbiu_adr_o(sbbiu_adr_sb),
977
        .sbbiu_cyc_o(sbbiu_cyc_sb),
978
        .sbbiu_stb_o(sbbiu_stb_sb),
979
        .sbbiu_we_o(sbbiu_we_sb),
980
        .sbbiu_sel_o(sbbiu_sel_sb),
981
        .sbbiu_cab_o(sbbiu_cab_sb),
982
        .sbbiu_dat_i(sbbiu_dat_biu),
983
        .sbbiu_ack_i(sbbiu_ack_biu),
984
        .sbbiu_err_i(sbbiu_err_biu)
985
);
986
 
987
//
988
// Instantiation of Debug Unit
989
//
990
or1200_du or1200_du(
991
        // RISC Internal Interface
992
        .clk(clk_i),
993
        .rst(rst_i),
994
        .dcpu_cycstb_i(dcpu_cycstb_cpu),
995
        .dcpu_we_i(dcpu_we_cpu),
996
        .dcpu_adr_i(dcpu_adr_cpu),
997
        .dcpu_dat_lsu(dcpu_dat_cpu),
998
        .dcpu_dat_dc(dcpu_dat_qmem),
999
        .icpu_cycstb_i(icpu_cycstb_cpu),
1000
        .ex_freeze(ex_freeze),
1001
        .branch_op(branch_op),
1002
        .ex_insn(ex_insn),
1003
        .id_pc(id_pc),
1004
        .du_dsr(du_dsr),
1005 142 marcus.erl
        .du_dmr1(du_dmr1),
1006 10 unneback
 
1007
        // For Trace buffer
1008
        .spr_dat_npc(spr_dat_npc),
1009
        .rf_dataw(rf_dataw),
1010
 
1011
        // DU's access to SPR unit
1012
        .du_stall(du_stall),
1013
        .du_addr(du_addr),
1014
        .du_dat_i(du_dat_cpu),
1015
        .du_dat_o(du_dat_du),
1016
        .du_read(du_read),
1017
        .du_write(du_write),
1018 142 marcus.erl
        .du_except_stop(du_except_stop),
1019 10 unneback
        .du_hwbkpt(du_hwbkpt),
1020
 
1021
        // Access to DU's SPRs
1022
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
1023
        .spr_write(spr_we),
1024
        .spr_addr(spr_addr),
1025
        .spr_dat_i(spr_dat_cpu),
1026
        .spr_dat_o(spr_dat_du),
1027
 
1028
        // External Debug Interface
1029
        .dbg_stall_i(dbg_stall_i),
1030
        .dbg_ewt_i(dbg_ewt_i),
1031
        .dbg_lss_o(dbg_lss_o),
1032
        .dbg_is_o(dbg_is_o),
1033
        .dbg_wp_o(dbg_wp_o),
1034
        .dbg_bp_o(dbg_bp_o),
1035
        .dbg_stb_i(dbg_stb_i),
1036
        .dbg_we_i(dbg_we_i),
1037
        .dbg_adr_i(dbg_adr_i),
1038
        .dbg_dat_i(dbg_dat_i),
1039
        .dbg_dat_o(dbg_dat_o),
1040
        .dbg_ack_o(dbg_ack_o)
1041
);
1042
 
1043
//
1044
// Programmable interrupt controller
1045
//
1046
or1200_pic or1200_pic(
1047
        // RISC Internal Interface
1048
        .clk(clk_i),
1049
        .rst(rst_i),
1050
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_PIC]),
1051
        .spr_write(spr_we),
1052
        .spr_addr(spr_addr),
1053
        .spr_dat_i(spr_dat_cpu),
1054
        .spr_dat_o(spr_dat_pic),
1055
        .pic_wakeup(pic_wakeup),
1056
        .intr(sig_int),
1057
 
1058
        // PIC Interface
1059
        .pic_int(pic_ints_i)
1060
);
1061
 
1062
//
1063
// Instantiation of Tick timer
1064
//
1065
or1200_tt or1200_tt(
1066
        // RISC Internal Interface
1067
        .clk(clk_i),
1068
        .rst(rst_i),
1069
        .du_stall(du_stall),
1070
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
1071
        .spr_write(spr_we),
1072
        .spr_addr(spr_addr),
1073
        .spr_dat_i(spr_dat_cpu),
1074
        .spr_dat_o(spr_dat_tt),
1075
        .intr(sig_tick)
1076
);
1077
 
1078
//
1079
// Instantiation of Power Management
1080
//
1081
or1200_pm or1200_pm(
1082
        // RISC Internal Interface
1083
        .clk(clk_i),
1084
        .rst(rst_i),
1085
        .pic_wakeup(pic_wakeup),
1086
        .spr_write(spr_we),
1087
        .spr_addr(spr_addr),
1088
        .spr_dat_i(spr_dat_cpu),
1089
        .spr_dat_o(spr_dat_pm),
1090
 
1091
        // Power Management Interface
1092
        .pm_cpustall(pm_cpustall_i),
1093
        .pm_clksd(pm_clksd_o),
1094
        .pm_dc_gate(pm_dc_gate_o),
1095
        .pm_ic_gate(pm_ic_gate_o),
1096
        .pm_dmmu_gate(pm_dmmu_gate_o),
1097
        .pm_immu_gate(pm_immu_gate_o),
1098
        .pm_tt_gate(pm_tt_gate_o),
1099
        .pm_cpu_gate(pm_cpu_gate_o),
1100
        .pm_wakeup(pm_wakeup_o),
1101
        .pm_lvolt(pm_lvolt_o)
1102
);
1103
 
1104
 
1105
endmodule

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