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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Blame information for rev 131

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//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200 Top Level                                            ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
9
////  OR1200 Top Level                                            ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
18
////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
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////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46
// $Log: not supported by cvs2svn $
47
// Revision 1.12  2004/04/05 08:29:57  lampret
48
// Merged branch_qmem into main tree.
49
//
50
// Revision 1.10.4.9  2004/02/11 01:40:11  lampret
51
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
52
//
53
// Revision 1.10.4.8  2004/01/17 21:14:14  simons
54
// Errors fixed.
55
//
56
// Revision 1.10.4.7  2004/01/17 19:06:38  simons
57
// Error fixed.
58
//
59
// Revision 1.10.4.6  2004/01/17 18:39:48  simons
60
// Error fixed.
61
//
62
// Revision 1.10.4.5  2004/01/15 06:46:38  markom
63
// interface to debug changed; no more opselect; stb-ack protocol
64
//
65
// Revision 1.10.4.4  2003/12/09 11:46:49  simons
66
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
67
//
68
// Revision 1.10.4.3  2003/12/05 00:08:44  lampret
69
// Fixed instantiation name.
70
//
71
// Revision 1.10.4.2  2003/07/11 01:10:35  lampret
72
// Added three missing wire declarations. No functional changes.
73
//
74
// Revision 1.10.4.1  2003/07/08 15:36:37  lampret
75
// Added embedded memory QMEM.
76
//
77
// Revision 1.10  2002/12/08 08:57:56  lampret
78
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
79
//
80
// Revision 1.9  2002/10/17 20:04:41  lampret
81
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
82
//
83
// Revision 1.8  2002/08/18 19:54:22  lampret
84
// Added store buffer.
85
//
86
// Revision 1.7  2002/07/14 22:17:17  lampret
87
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
88
//
89
// Revision 1.6  2002/03/29 15:16:56  lampret
90
// Some of the warnings fixed.
91
//
92
// Revision 1.5  2002/02/11 04:33:17  lampret
93
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
94
//
95
// Revision 1.4  2002/02/01 19:56:55  lampret
96
// Fixed combinational loops.
97
//
98
// Revision 1.3  2002/01/28 01:16:00  lampret
99
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
100
//
101
// Revision 1.2  2002/01/18 07:56:00  lampret
102
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
103
//
104
// Revision 1.1  2002/01/03 08:16:15  lampret
105
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
106
//
107
// Revision 1.13  2001/11/23 08:38:51  lampret
108
// Changed DSR/DRR behavior and exception detection.
109
//
110
// Revision 1.12  2001/11/20 00:57:22  lampret
111
// Fixed width of du_except.
112
//
113
// Revision 1.11  2001/11/18 08:36:28  lampret
114
// For GDB changed single stepping and disabled trap exception.
115
//
116
// Revision 1.10  2001/10/21 17:57:16  lampret
117
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
118
//
119
// Revision 1.9  2001/10/14 13:12:10  lampret
120
// MP3 version.
121
//
122
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
123
// no message
124
//
125
// Revision 1.4  2001/08/13 03:36:20  lampret
126
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
127
//
128
// Revision 1.3  2001/08/09 13:39:33  lampret
129
// Major clean-up.
130
//
131
// Revision 1.2  2001/07/22 03:31:54  lampret
132
// Fixed RAM's oen bug. Cache bypass under development.
133
//
134
// Revision 1.1  2001/07/20 00:46:21  lampret
135
// Development version of RTL. Libraries are missing.
136
//
137
//
138
 
139
// synopsys translate_off
140
`include "timescale.v"
141
// synopsys translate_on
142
`include "or1200_defines.v"
143
 
144
module or1200_top(
145
        // System
146
        clk_i, rst_i, pic_ints_i, clmode_i,
147
 
148
        // Instruction WISHBONE INTERFACE
149
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
150
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
151
`ifdef OR1200_WB_CAB
152
        iwb_cab_o,
153
`endif
154
`ifdef OR1200_WB_B3
155
        iwb_cti_o, iwb_bte_o,
156
`endif
157
        // Data WISHBONE INTERFACE
158
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
159
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
160
`ifdef OR1200_WB_CAB
161
        dwb_cab_o,
162
`endif
163
`ifdef OR1200_WB_B3
164
        dwb_cti_o, dwb_bte_o,
165
`endif
166
 
167
        // External Debug Interface
168
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
169
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
170
 
171
`ifdef OR1200_BIST
172
        // RAM BIST
173
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
174
`endif
175
        // Power Management
176
        pm_cpustall_i,
177
        pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
178
        pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
179
 
180
);
181
 
182
parameter dw = `OR1200_OPERAND_WIDTH;
183
parameter aw = `OR1200_OPERAND_WIDTH;
184
parameter ppic_ints = `OR1200_PIC_INTS;
185
 
186
//
187
// I/O
188
//
189
 
190
//
191
// System
192
//
193
input                   clk_i;
194
input                   rst_i;
195
input   [1:0]            clmode_i;       // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
196
input   [ppic_ints-1:0]  pic_ints_i;
197
 
198
//
199
// Instruction WISHBONE interface
200
//
201
input                   iwb_clk_i;      // clock input
202
input                   iwb_rst_i;      // reset input
203
input                   iwb_ack_i;      // normal termination
204
input                   iwb_err_i;      // termination w/ error
205
input                   iwb_rty_i;      // termination w/ retry
206
input   [dw-1:0] iwb_dat_i;      // input data bus
207
output                  iwb_cyc_o;      // cycle valid output
208
output  [aw-1:0] iwb_adr_o;      // address bus outputs
209
output                  iwb_stb_o;      // strobe output
210
output                  iwb_we_o;       // indicates write transfer
211
output  [3:0]            iwb_sel_o;      // byte select outputs
212
output  [dw-1:0] iwb_dat_o;      // output data bus
213
`ifdef OR1200_WB_CAB
214
output                  iwb_cab_o;      // indicates consecutive address burst
215
`endif
216
`ifdef OR1200_WB_B3
217
output  [2:0]            iwb_cti_o;      // cycle type identifier
218
output  [1:0]            iwb_bte_o;      // burst type extension
219
`endif
220
 
221
//
222
// Data WISHBONE interface
223
//
224
input                   dwb_clk_i;      // clock input
225
input                   dwb_rst_i;      // reset input
226
input                   dwb_ack_i;      // normal termination
227
input                   dwb_err_i;      // termination w/ error
228
input                   dwb_rty_i;      // termination w/ retry
229
input   [dw-1:0] dwb_dat_i;      // input data bus
230
output                  dwb_cyc_o;      // cycle valid output
231
output  [aw-1:0] dwb_adr_o;      // address bus outputs
232
output                  dwb_stb_o;      // strobe output
233
output                  dwb_we_o;       // indicates write transfer
234
output  [3:0]            dwb_sel_o;      // byte select outputs
235
output  [dw-1:0] dwb_dat_o;      // output data bus
236
`ifdef OR1200_WB_CAB
237
output                  dwb_cab_o;      // indicates consecutive address burst
238
`endif
239
`ifdef OR1200_WB_B3
240
output  [2:0]            dwb_cti_o;      // cycle type identifier
241
output  [1:0]            dwb_bte_o;      // burst type extension
242
`endif
243
 
244
//
245
// External Debug Interface
246
//
247
input                   dbg_stall_i;    // External Stall Input
248
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
249
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
250
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
251
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
252
output                  dbg_bp_o;       // Breakpoint Output
253
input                   dbg_stb_i;      // External Address/Data Strobe
254
input                   dbg_we_i;       // External Write Enable
255
input   [aw-1:0] dbg_adr_i;      // External Address Input
256
input   [dw-1:0] dbg_dat_i;      // External Data Input
257
output  [dw-1:0] dbg_dat_o;      // External Data Output
258
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
259
 
260
`ifdef OR1200_BIST
261
//
262
// RAM BIST
263
//
264
input mbist_si_i;
265
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
266
output mbist_so_o;
267
`endif
268
 
269
//
270
// Power Management
271
//
272
input                   pm_cpustall_i;
273
output  [3:0]            pm_clksd_o;
274
output                  pm_dc_gate_o;
275
output                  pm_ic_gate_o;
276
output                  pm_dmmu_gate_o;
277
output                  pm_immu_gate_o;
278
output                  pm_tt_gate_o;
279
output                  pm_cpu_gate_o;
280
output                  pm_wakeup_o;
281
output                  pm_lvolt_o;
282
 
283
 
284
//
285
// Internal wires and regs
286
//
287
 
288
//
289
// DC to SB
290
//
291
wire    [dw-1:0] dcsb_dat_dc;
292
wire    [aw-1:0] dcsb_adr_dc;
293
wire                    dcsb_cyc_dc;
294
wire                    dcsb_stb_dc;
295
wire                    dcsb_we_dc;
296
wire    [3:0]            dcsb_sel_dc;
297
wire                    dcsb_cab_dc;
298
wire    [dw-1:0] dcsb_dat_sb;
299
wire                    dcsb_ack_sb;
300
wire                    dcsb_err_sb;
301
 
302
//
303
// SB to BIU
304
//
305
wire    [dw-1:0] sbbiu_dat_sb;
306
wire    [aw-1:0] sbbiu_adr_sb;
307
wire                    sbbiu_cyc_sb;
308
wire                    sbbiu_stb_sb;
309
wire                    sbbiu_we_sb;
310
wire    [3:0]            sbbiu_sel_sb;
311
wire                    sbbiu_cab_sb;
312
wire    [dw-1:0] sbbiu_dat_biu;
313
wire                    sbbiu_ack_biu;
314
wire                    sbbiu_err_biu;
315
 
316
//
317
// IC to BIU
318
//
319
wire    [dw-1:0] icbiu_dat_ic;
320
wire    [aw-1:0] icbiu_adr_ic;
321
wire                    icbiu_cyc_ic;
322
wire                    icbiu_stb_ic;
323
wire                    icbiu_we_ic;
324
wire    [3:0]            icbiu_sel_ic;
325
wire    [3:0]            icbiu_tag_ic;
326
wire                    icbiu_cab_ic;
327
wire    [dw-1:0] icbiu_dat_biu;
328
wire                    icbiu_ack_biu;
329
wire                    icbiu_err_biu;
330
wire    [3:0]            icbiu_tag_biu;
331
 
332
//
333
// CPU's SPR access to various RISC units (shared wires)
334
//
335
wire                    supv;
336
wire    [aw-1:0] spr_addr;
337
wire    [dw-1:0] spr_dat_cpu;
338
wire    [31:0]           spr_cs;
339
wire                    spr_we;
340
 
341
//
342
// DMMU and CPU
343
//
344
wire                    dmmu_en;
345
wire    [31:0]           spr_dat_dmmu;
346
 
347
//
348
// DMMU and QMEM
349
//
350
wire                    qmemdmmu_err_qmem;
351
wire    [3:0]            qmemdmmu_tag_qmem;
352
wire    [aw-1:0] qmemdmmu_adr_dmmu;
353
wire                    qmemdmmu_cycstb_dmmu;
354
wire                    qmemdmmu_ci_dmmu;
355
 
356
//
357
// CPU and data memory subsystem
358
//
359
wire                    dc_en;
360
wire    [31:0]           dcpu_adr_cpu;
361
wire                    dcpu_cycstb_cpu;
362
wire                    dcpu_we_cpu;
363
wire    [3:0]            dcpu_sel_cpu;
364
wire    [3:0]            dcpu_tag_cpu;
365
wire    [31:0]           dcpu_dat_cpu;
366
wire    [31:0]           dcpu_dat_qmem;
367
wire                    dcpu_ack_qmem;
368
wire                    dcpu_rty_qmem;
369
wire                    dcpu_err_dmmu;
370
wire    [3:0]            dcpu_tag_dmmu;
371
 
372
//
373
// IMMU and CPU
374
//
375
wire                    immu_en;
376
wire    [31:0]           spr_dat_immu;
377
 
378
//
379
// CPU and insn memory subsystem
380
//
381
wire                    ic_en;
382
wire    [31:0]           icpu_adr_cpu;
383
wire                    icpu_cycstb_cpu;
384
wire    [3:0]            icpu_sel_cpu;
385
wire    [3:0]            icpu_tag_cpu;
386
wire    [31:0]           icpu_dat_qmem;
387
wire                    icpu_ack_qmem;
388
wire    [31:0]           icpu_adr_immu;
389
wire                    icpu_err_immu;
390
wire    [3:0]            icpu_tag_immu;
391
wire                    icpu_rty_immu;
392
 
393
//
394
// IMMU and QMEM
395
//
396
wire    [aw-1:0] qmemimmu_adr_immu;
397
wire                    qmemimmu_rty_qmem;
398
wire                    qmemimmu_err_qmem;
399
wire    [3:0]            qmemimmu_tag_qmem;
400
wire                    qmemimmu_cycstb_immu;
401
wire                    qmemimmu_ci_immu;
402
 
403
//
404
// QMEM and IC
405
//
406
wire    [aw-1:0] icqmem_adr_qmem;
407
wire                    icqmem_rty_ic;
408
wire                    icqmem_err_ic;
409
wire    [3:0]            icqmem_tag_ic;
410
wire                    icqmem_cycstb_qmem;
411
wire                    icqmem_ci_qmem;
412
wire    [31:0]           icqmem_dat_ic;
413
wire                    icqmem_ack_ic;
414
 
415
//
416
// QMEM and DC
417
//
418
wire    [aw-1:0] dcqmem_adr_qmem;
419
wire                    dcqmem_rty_dc;
420
wire                    dcqmem_err_dc;
421
wire    [3:0]            dcqmem_tag_dc;
422
wire                    dcqmem_cycstb_qmem;
423
wire                    dcqmem_ci_qmem;
424
wire    [31:0]           dcqmem_dat_dc;
425
wire    [31:0]           dcqmem_dat_qmem;
426
wire                    dcqmem_we_qmem;
427
wire    [3:0]            dcqmem_sel_qmem;
428
wire                    dcqmem_ack_dc;
429
 
430
//
431
// Connection between CPU and PIC
432
//
433
wire    [dw-1:0] spr_dat_pic;
434
wire                    pic_wakeup;
435
wire                    sig_int;
436
 
437
//
438
// Connection between CPU and PM
439
//
440
wire    [dw-1:0] spr_dat_pm;
441
 
442
//
443
// CPU and TT
444
//
445
wire    [dw-1:0] spr_dat_tt;
446
wire                    sig_tick;
447
 
448
//
449
// Debug port and caches/MMUs
450
//
451
wire    [dw-1:0] spr_dat_du;
452
wire                    du_stall;
453
wire    [dw-1:0] du_addr;
454
wire    [dw-1:0] du_dat_du;
455
wire                    du_read;
456
wire                    du_write;
457
wire    [12:0]           du_except;
458
wire    [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
459
wire    [dw-1:0] du_dat_cpu;
460
wire                    du_hwbkpt;
461
 
462
wire                    ex_freeze;
463
wire    [31:0]           ex_insn;
464
wire    [31:0]           id_pc;
465
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
466
wire    [31:0]           spr_dat_npc;
467
wire    [31:0]           rf_dataw;
468
 
469
`ifdef OR1200_BIST
470
//
471
// RAM BIST
472
//
473
wire                    mbist_immu_so;
474
wire                    mbist_ic_so;
475
wire                    mbist_dmmu_so;
476
wire                    mbist_dc_so;
477
wire      mbist_qmem_so;
478
wire                    mbist_immu_si = mbist_si_i;
479
wire                    mbist_ic_si = mbist_immu_so;
480
wire                    mbist_qmem_si = mbist_ic_so;
481
wire                    mbist_dmmu_si = mbist_qmem_so;
482
wire                    mbist_dc_si = mbist_dmmu_so;
483
assign                  mbist_so_o = mbist_dc_so;
484
`endif
485
 
486
wire  [3:0] icqmem_sel_qmem;
487
wire  [3:0] icqmem_tag_qmem;
488
wire  [3:0] dcqmem_tag_qmem;
489
 
490
//
491
// Instantiation of Instruction WISHBONE BIU
492
//
493
or1200_iwb_biu iwb_biu(
494
        // RISC clk, rst and clock control
495
        .clk(clk_i),
496
        .rst(rst_i),
497
        .clmode(clmode_i),
498
 
499
        // WISHBONE interface
500
        .wb_clk_i(iwb_clk_i),
501
        .wb_rst_i(iwb_rst_i),
502
        .wb_ack_i(iwb_ack_i),
503
        .wb_err_i(iwb_err_i),
504
        .wb_rty_i(iwb_rty_i),
505
        .wb_dat_i(iwb_dat_i),
506
        .wb_cyc_o(iwb_cyc_o),
507
        .wb_adr_o(iwb_adr_o),
508
        .wb_stb_o(iwb_stb_o),
509
        .wb_we_o(iwb_we_o),
510
        .wb_sel_o(iwb_sel_o),
511
        .wb_dat_o(iwb_dat_o),
512
`ifdef OR1200_WB_CAB
513
        .wb_cab_o(iwb_cab_o),
514
`endif
515
`ifdef OR1200_WB_B3
516
        .wb_cti_o(iwb_cti_o),
517
        .wb_bte_o(iwb_bte_o),
518
`endif
519
 
520
        // Internal RISC bus
521
        .biu_dat_i(icbiu_dat_ic),
522
        .biu_adr_i(icbiu_adr_ic),
523
        .biu_cyc_i(icbiu_cyc_ic),
524
        .biu_stb_i(icbiu_stb_ic),
525
        .biu_we_i(icbiu_we_ic),
526
        .biu_sel_i(icbiu_sel_ic),
527
        .biu_cab_i(icbiu_cab_ic),
528
        .biu_dat_o(icbiu_dat_biu),
529
        .biu_ack_o(icbiu_ack_biu),
530
        .biu_err_o(icbiu_err_biu)
531
);
532
 
533
//
534
// Instantiation of Data WISHBONE BIU
535
//
536
or1200_wb_biu dwb_biu(
537
        // RISC clk, rst and clock control
538
        .clk(clk_i),
539
        .rst(rst_i),
540
        .clmode(clmode_i),
541
 
542
        // WISHBONE interface
543
        .wb_clk_i(dwb_clk_i),
544
        .wb_rst_i(dwb_rst_i),
545
        .wb_ack_i(dwb_ack_i),
546
        .wb_err_i(dwb_err_i),
547
        .wb_rty_i(dwb_rty_i),
548
        .wb_dat_i(dwb_dat_i),
549
        .wb_cyc_o(dwb_cyc_o),
550
        .wb_adr_o(dwb_adr_o),
551
        .wb_stb_o(dwb_stb_o),
552
        .wb_we_o(dwb_we_o),
553
        .wb_sel_o(dwb_sel_o),
554
        .wb_dat_o(dwb_dat_o),
555
`ifdef OR1200_WB_CAB
556
        .wb_cab_o(dwb_cab_o),
557
`endif
558
`ifdef OR1200_WB_B3
559
        .wb_cti_o(dwb_cti_o),
560
        .wb_bte_o(dwb_bte_o),
561
`endif
562
 
563
        // Internal RISC bus
564
        .biu_dat_i(sbbiu_dat_sb),
565
        .biu_adr_i(sbbiu_adr_sb),
566
        .biu_cyc_i(sbbiu_cyc_sb),
567
        .biu_stb_i(sbbiu_stb_sb),
568
        .biu_we_i(sbbiu_we_sb),
569
        .biu_sel_i(sbbiu_sel_sb),
570
        .biu_cab_i(sbbiu_cab_sb),
571
        .biu_dat_o(sbbiu_dat_biu),
572
        .biu_ack_o(sbbiu_ack_biu),
573
        .biu_err_o(sbbiu_err_biu)
574
);
575
 
576
//
577
// Instantiation of IMMU
578
//
579
or1200_immu_top or1200_immu_top(
580
        // Rst and clk
581
        .clk(clk_i),
582
        .rst(rst_i),
583
 
584
`ifdef OR1200_BIST
585
        // RAM BIST
586
        .mbist_si_i(mbist_immu_si),
587
        .mbist_so_o(mbist_immu_so),
588
        .mbist_ctrl_i(mbist_ctrl_i),
589
`endif
590
 
591
        // CPU and IMMU
592
        .ic_en(ic_en),
593
        .immu_en(immu_en),
594
        .supv(supv),
595
        .icpu_adr_i(icpu_adr_cpu),
596
        .icpu_cycstb_i(icpu_cycstb_cpu),
597
        .icpu_adr_o(icpu_adr_immu),
598
        .icpu_tag_o(icpu_tag_immu),
599
        .icpu_rty_o(icpu_rty_immu),
600
        .icpu_err_o(icpu_err_immu),
601
 
602
        // SPR access
603
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
604
        .spr_write(spr_we),
605
        .spr_addr(spr_addr),
606
        .spr_dat_i(spr_dat_cpu),
607
        .spr_dat_o(spr_dat_immu),
608
 
609
        // QMEM and IMMU
610
        .qmemimmu_rty_i(qmemimmu_rty_qmem),
611
        .qmemimmu_err_i(qmemimmu_err_qmem),
612
        .qmemimmu_tag_i(qmemimmu_tag_qmem),
613
        .qmemimmu_adr_o(qmemimmu_adr_immu),
614
        .qmemimmu_cycstb_o(qmemimmu_cycstb_immu),
615
        .qmemimmu_ci_o(qmemimmu_ci_immu)
616
);
617
 
618
//
619
// Instantiation of Instruction Cache
620
//
621
or1200_ic_top or1200_ic_top(
622
        .clk(clk_i),
623
        .rst(rst_i),
624
 
625
`ifdef OR1200_BIST
626
        // RAM BIST
627
        .mbist_si_i(mbist_ic_si),
628
        .mbist_so_o(mbist_ic_so),
629
        .mbist_ctrl_i(mbist_ctrl_i),
630
`endif
631
 
632
        // IC and QMEM
633
        .ic_en(ic_en),
634
        .icqmem_adr_i(icqmem_adr_qmem),
635
        .icqmem_cycstb_i(icqmem_cycstb_qmem),
636
        .icqmem_ci_i(icqmem_ci_qmem),
637
        .icqmem_sel_i(icqmem_sel_qmem),
638
        .icqmem_tag_i(icqmem_tag_qmem),
639
        .icqmem_dat_o(icqmem_dat_ic),
640
        .icqmem_ack_o(icqmem_ack_ic),
641
        .icqmem_rty_o(icqmem_rty_ic),
642
        .icqmem_err_o(icqmem_err_ic),
643
        .icqmem_tag_o(icqmem_tag_ic),
644
 
645
        // SPR access
646
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
647
        .spr_write(spr_we),
648
        .spr_dat_i(spr_dat_cpu),
649
 
650
        // IC and BIU
651
        .icbiu_dat_o(icbiu_dat_ic),
652
        .icbiu_adr_o(icbiu_adr_ic),
653
        .icbiu_cyc_o(icbiu_cyc_ic),
654
        .icbiu_stb_o(icbiu_stb_ic),
655
        .icbiu_we_o(icbiu_we_ic),
656
        .icbiu_sel_o(icbiu_sel_ic),
657
        .icbiu_cab_o(icbiu_cab_ic),
658
        .icbiu_dat_i(icbiu_dat_biu),
659
        .icbiu_ack_i(icbiu_ack_biu),
660
        .icbiu_err_i(icbiu_err_biu)
661
);
662
 
663
//
664
// Instantiation of Instruction Cache
665
//
666
or1200_cpu or1200_cpu(
667
        .clk(clk_i),
668
        .rst(rst_i),
669
 
670
        // Connection QMEM and IFETCHER inside CPU
671
        .ic_en(ic_en),
672
        .icpu_adr_o(icpu_adr_cpu),
673
        .icpu_cycstb_o(icpu_cycstb_cpu),
674
        .icpu_sel_o(icpu_sel_cpu),
675
        .icpu_tag_o(icpu_tag_cpu),
676
        .icpu_dat_i(icpu_dat_qmem),
677
        .icpu_ack_i(icpu_ack_qmem),
678
        .icpu_rty_i(icpu_rty_immu),
679
        .icpu_adr_i(icpu_adr_immu),
680
        .icpu_err_i(icpu_err_immu),
681
        .icpu_tag_i(icpu_tag_immu),
682
 
683
        // Connection CPU to external Debug port
684
        .ex_freeze(ex_freeze),
685
        .ex_insn(ex_insn),
686
        .id_pc(id_pc),
687
        .branch_op(branch_op),
688
        .du_stall(du_stall),
689
        .du_addr(du_addr),
690
        .du_dat_du(du_dat_du),
691
        .du_read(du_read),
692
        .du_write(du_write),
693
        .du_dsr(du_dsr),
694
        .du_except(du_except),
695
        .du_dat_cpu(du_dat_cpu),
696
        .du_hwbkpt(du_hwbkpt),
697
        .rf_dataw(rf_dataw),
698
 
699
 
700
        // Connection IMMU and CPU internally
701
        .immu_en(immu_en),
702
 
703
        // Connection QMEM and CPU
704
        .dc_en(dc_en),
705
        .dcpu_adr_o(dcpu_adr_cpu),
706
        .dcpu_cycstb_o(dcpu_cycstb_cpu),
707
        .dcpu_we_o(dcpu_we_cpu),
708
        .dcpu_sel_o(dcpu_sel_cpu),
709
        .dcpu_tag_o(dcpu_tag_cpu),
710
        .dcpu_dat_o(dcpu_dat_cpu),
711
        .dcpu_dat_i(dcpu_dat_qmem),
712
        .dcpu_ack_i(dcpu_ack_qmem),
713
        .dcpu_rty_i(dcpu_rty_qmem),
714
        .dcpu_err_i(dcpu_err_dmmu),
715
        .dcpu_tag_i(dcpu_tag_dmmu),
716
 
717
        // Connection DMMU and CPU internally
718
        .dmmu_en(dmmu_en),
719
 
720
        // Connection PIC and CPU's EXCEPT
721
        .sig_int(sig_int),
722
        .sig_tick(sig_tick),
723
 
724
        // SPRs
725
        .supv(supv),
726
        .spr_addr(spr_addr),
727
        .spr_dat_cpu(spr_dat_cpu),
728
        .spr_dat_pic(spr_dat_pic),
729
        .spr_dat_tt(spr_dat_tt),
730
        .spr_dat_pm(spr_dat_pm),
731
        .spr_dat_dmmu(spr_dat_dmmu),
732
        .spr_dat_immu(spr_dat_immu),
733
        .spr_dat_du(spr_dat_du),
734
        .spr_dat_npc(spr_dat_npc),
735
        .spr_cs(spr_cs),
736
        .spr_we(spr_we)
737
);
738
 
739
//
740
// Instantiation of DMMU
741
//
742
or1200_dmmu_top or1200_dmmu_top(
743
        // Rst and clk
744
        .clk(clk_i),
745
        .rst(rst_i),
746
 
747
`ifdef OR1200_BIST
748
        // RAM BIST
749
        .mbist_si_i(mbist_dmmu_si),
750
        .mbist_so_o(mbist_dmmu_so),
751
        .mbist_ctrl_i(mbist_ctrl_i),
752
`endif
753
 
754
        // CPU i/f
755
        .dc_en(dc_en),
756
        .dmmu_en(dmmu_en),
757
        .supv(supv),
758
        .dcpu_adr_i(dcpu_adr_cpu),
759
        .dcpu_cycstb_i(dcpu_cycstb_cpu),
760
        .dcpu_we_i(dcpu_we_cpu),
761
        .dcpu_tag_o(dcpu_tag_dmmu),
762
        .dcpu_err_o(dcpu_err_dmmu),
763
 
764
        // SPR access
765
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DMMU]),
766
        .spr_write(spr_we),
767
        .spr_addr(spr_addr),
768
        .spr_dat_i(spr_dat_cpu),
769
        .spr_dat_o(spr_dat_dmmu),
770
 
771
        // QMEM and DMMU
772
        .qmemdmmu_err_i(qmemdmmu_err_qmem),
773
        .qmemdmmu_tag_i(qmemdmmu_tag_qmem),
774
        .qmemdmmu_adr_o(qmemdmmu_adr_dmmu),
775
        .qmemdmmu_cycstb_o(qmemdmmu_cycstb_dmmu),
776
        .qmemdmmu_ci_o(qmemdmmu_ci_dmmu)
777
);
778
 
779
//
780
// Instantiation of Data Cache
781
//
782
or1200_dc_top or1200_dc_top(
783
        .clk(clk_i),
784
        .rst(rst_i),
785
 
786
`ifdef OR1200_BIST
787
        // RAM BIST
788
        .mbist_si_i(mbist_dc_si),
789
        .mbist_so_o(mbist_dc_so),
790
        .mbist_ctrl_i(mbist_ctrl_i),
791
`endif
792
 
793
        // DC and QMEM
794
        .dc_en(dc_en),
795
        .dcqmem_adr_i(dcqmem_adr_qmem),
796
        .dcqmem_cycstb_i(dcqmem_cycstb_qmem),
797
        .dcqmem_ci_i(dcqmem_ci_qmem),
798
        .dcqmem_we_i(dcqmem_we_qmem),
799
        .dcqmem_sel_i(dcqmem_sel_qmem),
800
        .dcqmem_tag_i(dcqmem_tag_qmem),
801
        .dcqmem_dat_i(dcqmem_dat_qmem),
802
        .dcqmem_dat_o(dcqmem_dat_dc),
803
        .dcqmem_ack_o(dcqmem_ack_dc),
804
        .dcqmem_rty_o(dcqmem_rty_dc),
805
        .dcqmem_err_o(dcqmem_err_dc),
806
        .dcqmem_tag_o(dcqmem_tag_dc),
807
 
808
        // SPR access
809
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
810
        .spr_write(spr_we),
811
        .spr_dat_i(spr_dat_cpu),
812
 
813
        // DC and BIU
814
        .dcsb_dat_o(dcsb_dat_dc),
815
        .dcsb_adr_o(dcsb_adr_dc),
816
        .dcsb_cyc_o(dcsb_cyc_dc),
817
        .dcsb_stb_o(dcsb_stb_dc),
818
        .dcsb_we_o(dcsb_we_dc),
819
        .dcsb_sel_o(dcsb_sel_dc),
820
        .dcsb_cab_o(dcsb_cab_dc),
821
        .dcsb_dat_i(dcsb_dat_sb),
822
        .dcsb_ack_i(dcsb_ack_sb),
823
        .dcsb_err_i(dcsb_err_sb)
824
);
825
 
826
//
827
// Instantiation of embedded memory - qmem
828
//
829
or1200_qmem_top or1200_qmem_top(
830
        .clk(clk_i),
831
        .rst(rst_i),
832
 
833
`ifdef OR1200_BIST
834
        // RAM BIST
835
        .mbist_si_i(mbist_qmem_si),
836
        .mbist_so_o(mbist_qmem_so),
837
        .mbist_ctrl_i(mbist_ctrl_i),
838
`endif
839
 
840
        // QMEM and CPU/IMMU
841
        .qmemimmu_adr_i(qmemimmu_adr_immu),
842
        .qmemimmu_cycstb_i(qmemimmu_cycstb_immu),
843
        .qmemimmu_ci_i(qmemimmu_ci_immu),
844
        .qmemicpu_sel_i(icpu_sel_cpu),
845
        .qmemicpu_tag_i(icpu_tag_cpu),
846
        .qmemicpu_dat_o(icpu_dat_qmem),
847
        .qmemicpu_ack_o(icpu_ack_qmem),
848
        .qmemimmu_rty_o(qmemimmu_rty_qmem),
849
        .qmemimmu_err_o(qmemimmu_err_qmem),
850
        .qmemimmu_tag_o(qmemimmu_tag_qmem),
851
 
852
        // QMEM and IC
853
        .icqmem_adr_o(icqmem_adr_qmem),
854
        .icqmem_cycstb_o(icqmem_cycstb_qmem),
855
        .icqmem_ci_o(icqmem_ci_qmem),
856
        .icqmem_sel_o(icqmem_sel_qmem),
857
        .icqmem_tag_o(icqmem_tag_qmem),
858
        .icqmem_dat_i(icqmem_dat_ic),
859
        .icqmem_ack_i(icqmem_ack_ic),
860
        .icqmem_rty_i(icqmem_rty_ic),
861
        .icqmem_err_i(icqmem_err_ic),
862
        .icqmem_tag_i(icqmem_tag_ic),
863
 
864
        // QMEM and CPU/DMMU
865
        .qmemdmmu_adr_i(qmemdmmu_adr_dmmu),
866
        .qmemdmmu_cycstb_i(qmemdmmu_cycstb_dmmu),
867
        .qmemdmmu_ci_i(qmemdmmu_ci_dmmu),
868
        .qmemdcpu_we_i(dcpu_we_cpu),
869
        .qmemdcpu_sel_i(dcpu_sel_cpu),
870
        .qmemdcpu_tag_i(dcpu_tag_cpu),
871
        .qmemdcpu_dat_i(dcpu_dat_cpu),
872
        .qmemdcpu_dat_o(dcpu_dat_qmem),
873
        .qmemdcpu_ack_o(dcpu_ack_qmem),
874
        .qmemdcpu_rty_o(dcpu_rty_qmem),
875
        .qmemdmmu_err_o(qmemdmmu_err_qmem),
876
        .qmemdmmu_tag_o(qmemdmmu_tag_qmem),
877
 
878
        // QMEM and DC
879
        .dcqmem_adr_o(dcqmem_adr_qmem),
880
        .dcqmem_cycstb_o(dcqmem_cycstb_qmem),
881
        .dcqmem_ci_o(dcqmem_ci_qmem),
882
        .dcqmem_we_o(dcqmem_we_qmem),
883
        .dcqmem_sel_o(dcqmem_sel_qmem),
884
        .dcqmem_tag_o(dcqmem_tag_qmem),
885
        .dcqmem_dat_o(dcqmem_dat_qmem),
886
        .dcqmem_dat_i(dcqmem_dat_dc),
887
        .dcqmem_ack_i(dcqmem_ack_dc),
888
        .dcqmem_rty_i(dcqmem_rty_dc),
889
        .dcqmem_err_i(dcqmem_err_dc),
890
        .dcqmem_tag_i(dcqmem_tag_dc)
891
);
892
 
893
//
894
// Instantiation of Store Buffer
895
//
896
or1200_sb or1200_sb(
897
        // RISC clock, reset
898
        .clk(clk_i),
899
        .rst(rst_i),
900
 
901
        // Internal RISC bus (DC<->SB)
902
        .dcsb_dat_i(dcsb_dat_dc),
903
        .dcsb_adr_i(dcsb_adr_dc),
904
        .dcsb_cyc_i(dcsb_cyc_dc),
905
        .dcsb_stb_i(dcsb_stb_dc),
906
        .dcsb_we_i(dcsb_we_dc),
907
        .dcsb_sel_i(dcsb_sel_dc),
908
        .dcsb_cab_i(dcsb_cab_dc),
909
        .dcsb_dat_o(dcsb_dat_sb),
910
        .dcsb_ack_o(dcsb_ack_sb),
911
        .dcsb_err_o(dcsb_err_sb),
912
 
913
        // SB and BIU
914
        .sbbiu_dat_o(sbbiu_dat_sb),
915
        .sbbiu_adr_o(sbbiu_adr_sb),
916
        .sbbiu_cyc_o(sbbiu_cyc_sb),
917
        .sbbiu_stb_o(sbbiu_stb_sb),
918
        .sbbiu_we_o(sbbiu_we_sb),
919
        .sbbiu_sel_o(sbbiu_sel_sb),
920
        .sbbiu_cab_o(sbbiu_cab_sb),
921
        .sbbiu_dat_i(sbbiu_dat_biu),
922
        .sbbiu_ack_i(sbbiu_ack_biu),
923
        .sbbiu_err_i(sbbiu_err_biu)
924
);
925
 
926
//
927
// Instantiation of Debug Unit
928
//
929
or1200_du or1200_du(
930
        // RISC Internal Interface
931
        .clk(clk_i),
932
        .rst(rst_i),
933
        .dcpu_cycstb_i(dcpu_cycstb_cpu),
934
        .dcpu_we_i(dcpu_we_cpu),
935
        .dcpu_adr_i(dcpu_adr_cpu),
936
        .dcpu_dat_lsu(dcpu_dat_cpu),
937
        .dcpu_dat_dc(dcpu_dat_qmem),
938
        .icpu_cycstb_i(icpu_cycstb_cpu),
939
        .ex_freeze(ex_freeze),
940
        .branch_op(branch_op),
941
        .ex_insn(ex_insn),
942
        .id_pc(id_pc),
943
        .du_dsr(du_dsr),
944
 
945
        // For Trace buffer
946
        .spr_dat_npc(spr_dat_npc),
947
        .rf_dataw(rf_dataw),
948
 
949
        // DU's access to SPR unit
950
        .du_stall(du_stall),
951
        .du_addr(du_addr),
952
        .du_dat_i(du_dat_cpu),
953
        .du_dat_o(du_dat_du),
954
        .du_read(du_read),
955
        .du_write(du_write),
956
        .du_except(du_except),
957
        .du_hwbkpt(du_hwbkpt),
958
 
959
        // Access to DU's SPRs
960
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
961
        .spr_write(spr_we),
962
        .spr_addr(spr_addr),
963
        .spr_dat_i(spr_dat_cpu),
964
        .spr_dat_o(spr_dat_du),
965
 
966
        // External Debug Interface
967
        .dbg_stall_i(dbg_stall_i),
968
        .dbg_ewt_i(dbg_ewt_i),
969
        .dbg_lss_o(dbg_lss_o),
970
        .dbg_is_o(dbg_is_o),
971
        .dbg_wp_o(dbg_wp_o),
972
        .dbg_bp_o(dbg_bp_o),
973
        .dbg_stb_i(dbg_stb_i),
974
        .dbg_we_i(dbg_we_i),
975
        .dbg_adr_i(dbg_adr_i),
976
        .dbg_dat_i(dbg_dat_i),
977
        .dbg_dat_o(dbg_dat_o),
978
        .dbg_ack_o(dbg_ack_o)
979
);
980
 
981
//
982
// Programmable interrupt controller
983
//
984
or1200_pic or1200_pic(
985
        // RISC Internal Interface
986
        .clk(clk_i),
987
        .rst(rst_i),
988
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_PIC]),
989
        .spr_write(spr_we),
990
        .spr_addr(spr_addr),
991
        .spr_dat_i(spr_dat_cpu),
992
        .spr_dat_o(spr_dat_pic),
993
        .pic_wakeup(pic_wakeup),
994
        .intr(sig_int),
995
 
996
        // PIC Interface
997
        .pic_int(pic_ints_i)
998
);
999
 
1000
//
1001
// Instantiation of Tick timer
1002
//
1003
or1200_tt or1200_tt(
1004
        // RISC Internal Interface
1005
        .clk(clk_i),
1006
        .rst(rst_i),
1007
        .du_stall(du_stall),
1008
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
1009
        .spr_write(spr_we),
1010
        .spr_addr(spr_addr),
1011
        .spr_dat_i(spr_dat_cpu),
1012
        .spr_dat_o(spr_dat_tt),
1013
        .intr(sig_tick)
1014
);
1015
 
1016
//
1017
// Instantiation of Power Management
1018
//
1019
or1200_pm or1200_pm(
1020
        // RISC Internal Interface
1021
        .clk(clk_i),
1022
        .rst(rst_i),
1023
        .pic_wakeup(pic_wakeup),
1024
        .spr_write(spr_we),
1025
        .spr_addr(spr_addr),
1026
        .spr_dat_i(spr_dat_cpu),
1027
        .spr_dat_o(spr_dat_pm),
1028
 
1029
        // Power Management Interface
1030
        .pm_cpustall(pm_cpustall_i),
1031
        .pm_clksd(pm_clksd_o),
1032
        .pm_dc_gate(pm_dc_gate_o),
1033
        .pm_ic_gate(pm_ic_gate_o),
1034
        .pm_dmmu_gate(pm_dmmu_gate_o),
1035
        .pm_immu_gate(pm_immu_gate_o),
1036
        .pm_tt_gate(pm_tt_gate_o),
1037
        .pm_cpu_gate(pm_cpu_gate_o),
1038
        .pm_wakeup(pm_wakeup_o),
1039
        .pm_lvolt(pm_lvolt_o)
1040
);
1041
 
1042
 
1043
endmodule

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