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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tpram_32x32.v] - Blame information for rev 146

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1 10 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Generic Two-Port Synchronous RAM                            ////
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////                                                              ////
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////  This file is part of memory library available from          ////
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////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
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////                                                              ////
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////  Description                                                 ////
9
////  This block is a wrapper with common two-port                ////
10
////  synchronous memory interface for different                  ////
11
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
12
////  interface it also provides behavioral model of generic      ////
13
////  two-port synchronous RAM.                                   ////
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////  It should be used in all OPENCORES designs that want to be  ////
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////  portable accross different target technologies and          ////
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////  independent of target memory.                               ////
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////                                                              ////
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////  Supported ASIC RAMs are:                                    ////
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////  - Artisan Double-Port Sync RAM                              ////
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////  - Avant! Two-Port Sync RAM (*)                              ////
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////  - Virage 2-port Sync RAM                                    ////
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////                                                              ////
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////  Supported FPGA RAMs are:                                    ////
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////  - Xilinx Virtex RAMB16                                      ////
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////  - Xilinx Virtex RAMB4                                       ////
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////  - Altera LPM                                                ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - fix Avant!                                               ////
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////   - xilinx rams need external tri-state logic                ////
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////   - add additional RAMs (VS etc)                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
62
//
63
// CVS Revision History
64
//
65 142 marcus.erl
// $Log: or1200_tpram_32x32.v,v $
66
// Revision 2.0  2010/06/30 11:00:00  ORSoC
67
// Minor update: 
68
// Coding style changed.
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//
70
// Revision 1.5  2005/10/19 11:37:56  jcastillo
71
// Added support for RAMB16 Xilinx4/Spartan3 primitives
72
//
73 10 unneback
// Revision 1.4  2004/06/08 18:15:48  lampret
74
// Changed behavior of the simulation generic models
75
//
76
// Revision 1.3  2004/04/05 08:29:57  lampret
77
// Merged branch_qmem into main tree.
78
//
79
// Revision 1.2.4.1  2003/07/08 15:36:37  lampret
80
// Added embedded memory QMEM.
81
//
82
// Revision 1.2  2003/04/07 01:19:07  lampret
83
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
84
//
85
// Revision 1.1  2002/01/03 08:16:15  lampret
86
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
87
//
88
// Revision 1.7  2001/10/21 17:57:16  lampret
89
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
90
//
91
// Revision 1.6  2001/10/14 13:12:09  lampret
92
// MP3 version.
93
//
94
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
96
//
97
// Revision 1.1  2001/08/09 13:39:33  lampret
98
// Major clean-up.
99
//
100
// Revision 1.2  2001/07/30 05:38:02  lampret
101
// Adding empty directories required by HDL coding guidelines
102
//
103
//
104
 
105
// synopsys translate_off
106
`include "timescale.v"
107
// synopsys translate_on
108
`include "or1200_defines.v"
109
 
110
module or1200_tpram_32x32(
111
        // Generic synchronous two-port RAM interface
112
        clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a,
113
        clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b
114
);
115
 
116
//
117
// Default address and data buses width
118
//
119
parameter aw = 5;
120
parameter dw = 32;
121
 
122
//
123
// Generic synchronous two-port RAM interface
124
//
125
input                   clk_a;  // Clock
126
input                   rst_a;  // Reset
127
input                   ce_a;   // Chip enable input
128
input                   we_a;   // Write enable input
129
input                   oe_a;   // Output enable input
130
input   [aw-1:0] addr_a; // address bus inputs
131
input   [dw-1:0] di_a;   // input data bus
132
output  [dw-1:0] do_a;   // output data bus
133
input                   clk_b;  // Clock
134
input                   rst_b;  // Reset
135
input                   ce_b;   // Chip enable input
136
input                   we_b;   // Write enable input
137
input                   oe_b;   // Output enable input
138
input   [aw-1:0] addr_b; // address bus inputs
139
input   [dw-1:0] di_b;   // input data bus
140
output  [dw-1:0] do_b;   // output data bus
141
 
142
//
143
// Internal wires and registers
144
//
145
 
146
 
147
`ifdef OR1200_ARTISAN_SDP
148
 
149
//
150
// Instantiation of ASIC memory:
151
//
152
// Artisan Synchronous Double-Port RAM (ra2sh)
153
//
154
`ifdef UNUSED
155
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
156
`else
157
art_hsdp_32x32 artisan_sdp(
158
`endif
159
        .qa(do_a),
160
        .clka(clk_a),
161
        .cena(~ce_a),
162
        .wena(~we_a),
163
        .aa(addr_a),
164
        .da(di_a),
165
        .oena(~oe_a),
166
        .qb(do_b),
167
        .clkb(clk_b),
168
        .cenb(~ce_b),
169
        .wenb(~we_b),
170
        .ab(addr_b),
171
        .db(di_b),
172
        .oenb(~oe_b)
173
);
174
 
175
`else
176
 
177
`ifdef OR1200_AVANT_ATP
178
 
179
//
180
// Instantiation of ASIC memory:
181
//
182
// Avant! Asynchronous Two-Port RAM
183
//
184
avant_atp avant_atp(
185
        .web(~we),
186
        .reb(),
187
        .oeb(~oe),
188
        .rcsb(),
189
        .wcsb(),
190
        .ra(addr),
191
        .wa(addr),
192
        .di(di),
193
        .doq(doq)
194
);
195
 
196
`else
197
 
198
`ifdef OR1200_VIRAGE_STP
199
 
200
//
201
// Instantiation of ASIC memory:
202
//
203
// Virage Synchronous 2-port R/W RAM
204
//
205
virage_stp virage_stp(
206
        .QA(do_a),
207
        .QB(do_b),
208
 
209
        .ADRA(addr_a),
210
        .DA(di_a),
211
        .WEA(we_a),
212
        .OEA(oe_a),
213
        .MEA(ce_a),
214
        .CLKA(clk_a),
215
 
216
        .ADRB(adr_b),
217
        .DB(di_b),
218
        .WEB(we_b),
219
        .OEB(oe_b),
220
        .MEB(ce_b),
221
        .CLKB(clk_b)
222
);
223
 
224
`else
225
 
226
`ifdef OR1200_XILINX_RAMB4
227
 
228
//
229
// Instantiation of FPGA memory:
230
//
231
// Virtex/Spartan2
232
//
233
 
234
//
235
// Block 0
236
//
237
RAMB4_S16_S16 ramb4_s16_s16_0(
238
        .CLKA(clk_a),
239 142 marcus.erl
        .RSTA(1'b0),
240 10 unneback
        .ADDRA(addr_a),
241
        .DIA(di_a[15:0]),
242
        .ENA(ce_a),
243
        .WEA(we_a),
244
        .DOA(do_a[15:0]),
245
 
246
        .CLKB(clk_b),
247 142 marcus.erl
        .RSTB(1'b0),
248 10 unneback
        .ADDRB(addr_b),
249
        .DIB(di_b[15:0]),
250
        .ENB(ce_b),
251
        .WEB(we_b),
252
        .DOB(do_b[15:0])
253
);
254
 
255
//
256
// Block 1
257
//
258
RAMB4_S16_S16 ramb4_s16_s16_1(
259
        .CLKA(clk_a),
260 142 marcus.erl
        .RSTA(1'b0),
261 10 unneback
        .ADDRA(addr_a),
262
        .DIA(di_a[31:16]),
263
        .ENA(ce_a),
264
        .WEA(we_a),
265
        .DOA(do_a[31:16]),
266
 
267
        .CLKB(clk_b),
268 142 marcus.erl
        .RSTB(1'b0),
269 10 unneback
        .ADDRB(addr_b),
270
        .DIB(di_b[31:16]),
271
        .ENB(ce_b),
272
        .WEB(we_b),
273
        .DOB(do_b[31:16])
274
);
275
 
276
`else
277
 
278
`ifdef OR1200_XILINX_RAMB16
279
 
280
//
281
// Instantiation of FPGA memory:
282
//
283
// Virtex4/Spartan3E
284
//
285
// Added By Nir Mor
286
//
287
 
288
RAMB16_S36_S36 ramb16_s36_s36(
289
        .CLKA(clk_a),
290 142 marcus.erl
        .SSRA(1'b0),
291 10 unneback
        .ADDRA({4'b0000,addr_a}),
292
        .DIA(di_a),
293
        .DIPA(4'h0),
294
        .ENA(ce_a),
295
        .WEA(we_a),
296
        .DOA(do_a),
297
        .DOPA(),
298
 
299
        .CLKB(clk_b),
300 142 marcus.erl
        .SSRB(1'b0),
301 10 unneback
        .ADDRB({4'b0000,addr_b}),
302
        .DIB(di_b),
303
        .DIPB(4'h0),
304
        .ENB(ce_b),
305
        .WEB(we_b),
306
        .DOB(do_b),
307
        .DOPB()
308
);
309
 
310
`else
311
 
312
`ifdef OR1200_ALTERA_LPM_XXX
313
 
314
//
315
// Instantiation of FPGA memory:
316
//
317
// Altera LPM
318
//
319
// Added By Jamil Khatib
320
//
321
altqpram altqpram_component (
322
        .wraddress_a (addr_a),
323
        .inclocken_a (ce_a),
324
        .wraddress_b (addr_b),
325
        .wren_a (we_a),
326
        .inclocken_b (ce_b),
327
        .wren_b (we_b),
328 142 marcus.erl
        .inaclr_a (1'b0),
329
        .inaclr_b (1'b0),
330 10 unneback
        .inclock_a (clk_a),
331
        .inclock_b (clk_b),
332
        .data_a (di_a),
333
        .data_b (di_b),
334
        .q_a (do_a),
335
        .q_b (do_b)
336
);
337
 
338
defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",
339
        altqpram_component.width_write_a = dw,
340
        altqpram_component.widthad_write_a = aw,
341
        altqpram_component.numwords_write_a = dw,
342
        altqpram_component.width_read_a = dw,
343
        altqpram_component.widthad_read_a = aw,
344
        altqpram_component.numwords_read_a = dw,
345
        altqpram_component.width_write_b = dw,
346
        altqpram_component.widthad_write_b = aw,
347
        altqpram_component.numwords_write_b = dw,
348
        altqpram_component.width_read_b = dw,
349
        altqpram_component.widthad_read_b = aw,
350
        altqpram_component.numwords_read_b = dw,
351
        altqpram_component.indata_reg_a = "INCLOCK_A",
352
        altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",
353
        altqpram_component.outdata_reg_a = "INCLOCK_A",
354
        altqpram_component.indata_reg_b = "INCLOCK_B",
355
        altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",
356
        altqpram_component.outdata_reg_b = "INCLOCK_B",
357
        altqpram_component.indata_aclr_a = "INACLR_A",
358
        altqpram_component.wraddress_aclr_a = "INACLR_A",
359
        altqpram_component.wrcontrol_aclr_a = "INACLR_A",
360
        altqpram_component.outdata_aclr_a = "INACLR_A",
361
        altqpram_component.indata_aclr_b = "NONE",
362
        altqpram_component.wraddress_aclr_b = "NONE",
363
        altqpram_component.wrcontrol_aclr_b = "NONE",
364
        altqpram_component.outdata_aclr_b = "INACLR_B",
365
        altqpram_component.lpm_hint = "USE_ESB=ON";
366
        //examplar attribute altqpram_component NOOPT TRUE
367
 
368
`else
369
 
370
//
371
// Generic two-port synchronous RAM model
372
//
373
 
374
//
375
// Generic RAM's registers and wires
376
//
377
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
378
reg     [aw-1:0] addr_a_reg;             // RAM read address register
379
reg     [aw-1:0] addr_b_reg;             // RAM read address register
380
 
381
//
382
// Data output drivers
383
//
384
assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
385
assign do_b = (oe_b) ? mem[addr_b_reg] : {dw{1'b0}};
386
 
387
//
388
// RAM write
389
//
390
always @(posedge clk_a)
391
        if (ce_a && we_a)
392
                mem[addr_a] <= #1 di_a;
393
 
394
//
395
// RAM write
396
//
397
always @(posedge clk_b)
398
        if (ce_b && we_b)
399
                mem[addr_b] <= #1 di_b;
400
 
401
//
402
// RAM read address register
403
//
404
always @(posedge clk_a or posedge rst_a)
405
        if (rst_a)
406
                addr_a_reg <= #1 {aw{1'b0}};
407
        else if (ce_a)
408
                addr_a_reg <= #1 addr_a;
409
 
410
//
411
// RAM read address register
412
//
413
always @(posedge clk_b or posedge rst_b)
414
        if (rst_b)
415
                addr_b_reg <= #1 {aw{1'b0}};
416
        else if (ce_b)
417
                addr_b_reg <= #1 addr_b;
418
 
419
`endif  // !OR1200_ALTERA_LPM
420
`endif  // !OR1200_XILINX_RAMB16
421
`endif  // !OR1200_XILINX_RAMB4
422
`endif  // !OR1200_VIRAGE_STP
423
`endif  // !OR1200_AVANT_ATP
424
`endif  // !OR1200_ARTISAN_SDP
425
 
426
endmodule

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