OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tt.v] - Blame information for rev 588

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Tick Timer                                         ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  TT according to OR1K architectural specification.           ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   None                                                       ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
 
45
// synopsys translate_off
46
`include "timescale.v"
47
// synopsys translate_on
48
`include "or1200_defines.v"
49
 
50
module or1200_tt(
51
        // RISC Internal Interface
52
        clk, rst, du_stall,
53
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
54
        intr
55
);
56
 
57
//
58
// RISC Internal Interface
59
//
60
input           clk;            // Clock
61
input           rst;            // Reset
62
input           du_stall;       // DU stall
63
input           spr_cs;         // SPR CS
64
input           spr_write;      // SPR Write
65
input   [31:0]   spr_addr;       // SPR Address
66
input   [31:0]   spr_dat_i;      // SPR Write Data
67
output  [31:0]   spr_dat_o;      // SPR Read Data
68
output          intr;           // Interrupt output
69
 
70
`ifdef OR1200_TT_IMPLEMENTED
71
 
72
//
73
// TT Mode Register bits (or no register)
74
//
75
`ifdef OR1200_TT_TTMR
76
reg     [31:0]   ttmr;   // TTMR bits
77
`else
78
wire    [31:0]   ttmr;   // No TTMR register
79
`endif
80
 
81
//
82
// TT Count Register bits (or no register)
83
//
84
`ifdef OR1200_TT_TTCR
85
reg     [31:0]   ttcr;   // TTCR bits
86
`else
87
wire    [31:0]   ttcr;   // No TTCR register
88
`endif
89
 
90
//
91
// Internal wires & regs
92
//
93
wire            ttmr_sel;       // TTMR select
94
wire            ttcr_sel;       // TTCR select
95
wire            match;          // Asserted when TTMR[TP]
96
                                // is equal to TTCR[27:0]
97
wire            restart;        // Restart counter when asserted
98
wire            stop;           // Stop counter when asserted
99
reg     [31:0]   spr_dat_o;      // SPR data out
100
 
101
//
102
// TT registers address decoder
103
//
104
assign ttmr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
105
assign ttcr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
106
 
107
//
108
// Write to TTMR or update of TTMR[IP] bit
109
//
110
`ifdef OR1200_TT_TTMR
111 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
112
        if (rst == `OR1200_RST_VALUE)
113 10 unneback
                ttmr <= 32'b0;
114
        else if (ttmr_sel && spr_write)
115 258 julius
                ttmr <=  spr_dat_i;
116 10 unneback
        else if (ttmr[`OR1200_TT_TTMR_IE])
117 258 julius
                ttmr[`OR1200_TT_TTMR_IP] <=  ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);
118 10 unneback
`else
119
assign ttmr = {2'b11, 30'b0};    // TTMR[M] = 0x3
120
`endif
121
 
122
//
123
// Write to or increment of TTCR
124
//
125
`ifdef OR1200_TT_TTCR
126 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
127
        if (rst == `OR1200_RST_VALUE)
128 10 unneback
                ttcr <= 32'b0;
129
        else if (restart)
130 258 julius
                ttcr <=  32'b0;
131 10 unneback
        else if (ttcr_sel && spr_write)
132 258 julius
                ttcr <=  spr_dat_i;
133 10 unneback
        else if (!stop)
134 258 julius
                ttcr <=  ttcr + 32'd1;
135 10 unneback
`else
136
assign ttcr = 32'b0;
137
`endif
138
 
139
//
140
// Read TT registers
141
//
142
always @(spr_addr or ttmr or ttcr)
143
        case (spr_addr[`OR1200_TTOFS_BITS])     // synopsys parallel_case
144
`ifdef OR1200_TT_READREGS
145
                `OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;
146
`endif
147
                default: spr_dat_o = ttcr;
148
        endcase
149
 
150
//
151
// A match when TTMR[TP] is equal to TTCR[27:0]
152
//
153
assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
154
 
155
//
156
// Restart when match and TTMR[M]==0x1
157
//
158
assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);
159
 
160
//
161
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
162
//
163
assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
164
 
165
//
166
// Generate an interrupt request
167
//
168
assign intr = ttmr[`OR1200_TT_TTMR_IP];
169
 
170
`else
171
 
172
//
173
// When TT is not implemented, drive all outputs as would when TT is disabled
174
//
175
assign intr = 1'b0;
176
 
177
//
178
// Read TT registers
179
//
180
`ifdef OR1200_TT_READREGS
181
assign spr_dat_o = 32'b0;
182
`endif
183
 
184
`endif
185
 
186
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.