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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's WISHBONE BIU                                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Implements WISHBONE interface                               ////
////                                                              ////
////  To Do:                                                      ////
////   - if biu_cyc/stb are deasserted and wb_ack_i is asserted   ////
////   and this happens even before aborted_r is asssrted,        ////
////   wb_ack_i will be delivered even though transfer is         ////
////   internally considered already aborted. However most        ////
////   wb_ack_i are externally registered and delayed. Normally   ////
////   this shouldn't cause any problems.                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_wb_biu.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Structure reordered and bugs fixed. 
//
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
//
// Revision 1.6  2003/04/07 20:57:46  lampret
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
//
// Revision 1.5  2002/12/08 08:57:56  lampret
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
//
// Revision 1.4  2002/09/16 03:09:16  lampret
// Fixed a combinational loop.
//
// Revision 1.3  2002/08/12 05:31:37  lampret
// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
//
// Revision 1.2  2002/07/14 22:17:17  lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12  2001/11/22 13:42:51  lampret
// Added wb_cyc_o assignment after it was removed by accident.
//
// Revision 1.11  2001/11/20 21:28:10  lampret
// Added optional sampling of inputs.
//
// Revision 1.10  2001/11/18 11:32:00  lampret
// OR1200_REGISTERED_OUTPUTS can now be enabled.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:23  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_wb_biu(
        // RISC clock, reset and clock control
        clk, rst, clmode,
 
        // WISHBONE interface
        wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
        wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
`ifdef OR1200_WB_CAB
        wb_cab_o,
`endif
`ifdef OR1200_WB_B3
        wb_cti_o, wb_bte_o,
`endif
 
        // Internal RISC bus
        biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
        biu_dat_o, biu_ack_o, biu_err_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// RISC clock, reset and clock control
//
input                           clk;            // RISC clock
input                           rst;            // RISC reset
input   [1:0]                    clmode;         // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
 
//
// WISHBONE interface
//
input                           wb_clk_i;       // clock input
input                           wb_rst_i;       // reset input
input                           wb_ack_i;       // normal termination
input                           wb_err_i;       // termination w/ error
input                           wb_rty_i;       // termination w/ retry
input   [dw-1:0]         wb_dat_i;       // input data bus
output                          wb_cyc_o;       // cycle valid output
output  [aw-1:0]         wb_adr_o;       // address bus outputs
output                          wb_stb_o;       // strobe output
output                          wb_we_o;        // indicates write transfer
output  [3:0]                    wb_sel_o;       // byte select outputs
output  [dw-1:0]         wb_dat_o;       // output data bus
`ifdef OR1200_WB_CAB
output                          wb_cab_o;       // consecutive address burst
`endif
`ifdef OR1200_WB_B3
output  [2:0]                    wb_cti_o;       // cycle type identifier
output  [1:0]                    wb_bte_o;       // burst type extension
`endif
 
//
// Internal RISC interface
//
input   [dw-1:0]         biu_dat_i;      // input data bus
input   [aw-1:0]         biu_adr_i;      // address bus
input                           biu_cyc_i;      // WB cycle
input                           biu_stb_i;      // WB strobe
input                           biu_we_i;       // WB write enable
input                           biu_cab_i;      // CAB input
input   [3:0]                    biu_sel_i;      // byte selects
output  [31:0]                   biu_dat_o;      // output data bus
output                          biu_ack_o;      // ack output
output                          biu_err_o;      // err output
 
//
// Registers
//
wire                            wb_ack;         // normal termination
reg     [aw-1:0]         wb_adr_o;       // address bus outputs
reg                             wb_cyc_o;       // cycle output
reg                             wb_stb_o;       // strobe output
reg                             wb_we_o;        // indicates write transfer
reg     [3:0]                    wb_sel_o;       // byte select outputs
`ifdef OR1200_WB_CAB
reg                             wb_cab_o;       // CAB output
`endif
`ifdef OR1200_WB_B3
reg     [2:0]                    wb_cti_o;       // cycle type identifier
reg     [1:0]                    wb_bte_o;       // burst type extension
`endif
reg     [dw-1:0]         wb_dat_o;       // output data bus
 
`ifdef OR1200_WB_RETRY
reg     [`OR1200_WB_RETRY-1:0]   retry_cnt;      // Retry counter
`else
wire                            retry_cnt       = 1'b0;
`endif
`ifdef OR1200_WB_B3
reg     [1:0]                    burst_len;      // burst counter
`endif
 
reg                             biu_stb_reg;    // WB strobe
wire                            biu_stb;        // WB strobe
reg                             wb_cyc_nxt;     // next WB cycle value
reg                             wb_stb_nxt;     // next WB strobe value
reg     [2:0]                    wb_cti_nxt;     // next cycle type identifier value
 
reg                             wb_ack_cnt;     // WB ack toggle counter
reg                             wb_err_cnt;     // WB err toggle counter
reg                             wb_rty_cnt;     // WB rty toggle counter
reg                             biu_ack_cnt;    // BIU ack toggle counter
reg                             biu_err_cnt;    // BIU err toggle counter
reg                             biu_rty_cnt;    // BIU rty toggle counter
wire                            biu_rty;        // BIU rty indicator
 
reg     [1:0]                    wb_fsm_state_cur;       // WB FSM - surrent state
reg     [1:0]                    wb_fsm_state_nxt;       // WB FSM - next state
wire    [1:0]                    wb_fsm_idle     = 2'h0; // WB FSM state - IDLE
wire    [1:0]                    wb_fsm_trans    = 2'h1; // WB FSM state - normal TRANSFER
wire    [1:0]                    wb_fsm_last     = 2'h2; // EB FSM state - LAST transfer
 
//
// WISHBONE I/F <-> Internal RISC I/F conversion
//
//assign wb_ack = wb_ack_i;
assign wb_ack = wb_ack_i && !wb_err_i && !wb_rty_i;
 
//
// WB FSM - register part
// 
always @(posedge wb_clk_i or posedge wb_rst_i) begin
        if (wb_rst_i)
                wb_fsm_state_cur <= #1 wb_fsm_idle;
        else
                wb_fsm_state_cur <= #1 wb_fsm_state_nxt;
end
 
//
// WB burst tength counter
// 
always @(posedge wb_clk_i or posedge wb_rst_i) begin
        if (wb_rst_i) begin
                burst_len <= #1 2'h0;
        end
        else begin
                // burst counter
                if (wb_fsm_state_cur == wb_fsm_idle)
                        burst_len <= #1 2'h2;
                else if (wb_stb_o && wb_ack)
                        burst_len <= #1 burst_len - 1'b1;
        end
end
 
// 
// WB FSM - combinatorial part
// 
always @(wb_fsm_state_cur or burst_len or
         wb_err_i or wb_rty_i or wb_ack or wb_cti_o or wb_sel_o or wb_stb_o or wb_we_o or
         biu_cyc_i or biu_stb or biu_cab_i or biu_sel_i or biu_we_i) begin
// States of WISHBONE Finite State Machine
        case(wb_fsm_state_cur)
        // IDLE 
        wb_fsm_idle : begin
                wb_cyc_nxt = biu_cyc_i && biu_stb;
                wb_stb_nxt = biu_cyc_i && biu_stb;
                wb_cti_nxt = {!biu_cab_i, 1'b1, !biu_cab_i};
                if (biu_cyc_i && biu_stb)
                        wb_fsm_state_nxt = wb_fsm_trans;
                else
                        wb_fsm_state_nxt = wb_fsm_idle;
        end
        // normal TRANSFER
        wb_fsm_trans : begin
                wb_cyc_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
                wb_stb_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !wb_ack || !wb_err_i && !wb_rty_i && wb_cti_o == 3'b010 && !wb_we_o;
                wb_cti_nxt[2] = wb_stb_o && wb_ack && burst_len == 'h0 || wb_cti_o[2];
                wb_cti_nxt[1] = 1'b1  ;
                wb_cti_nxt[0] = wb_stb_o && wb_ack && burst_len == 'h0 || wb_cti_o[0];
                //if ((!biu_cyc_i || !biu_stb || !biu_cab_i) && wb_cti_o == 3'b010  || biu_sel_i != wb_sel_o || biu_we_i != wb_we_o)
                if ((!biu_cyc_i || !biu_stb || !biu_cab_i || biu_sel_i != wb_sel_o || biu_we_i != wb_we_o) && wb_cti_o == 3'b010)
                        wb_fsm_state_nxt = wb_fsm_last;
                else if ((wb_err_i || wb_rty_i || wb_ack && wb_cti_o == 3'b111) && wb_stb_o)
                        wb_fsm_state_nxt = wb_fsm_idle;
                else
                        wb_fsm_state_nxt = wb_fsm_trans;
        end
        // LAST transfer
        wb_fsm_last : begin
                wb_cyc_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
                wb_stb_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
                wb_cti_nxt[2] = wb_ack && wb_stb_o || wb_cti_o[2];
                wb_cti_nxt[1] = 1'b1                  ;
                wb_cti_nxt[0] = wb_ack && wb_stb_o || wb_cti_o[0];
                if ((wb_err_i || wb_rty_i || wb_ack && wb_cti_o == 3'b111) && wb_stb_o)
                        wb_fsm_state_nxt = wb_fsm_idle;
                else
                        wb_fsm_state_nxt = wb_fsm_last;
        end
        // default state
        default:begin
                wb_cyc_nxt = 1'bx;
                wb_stb_nxt = 1'bx;
                wb_cti_nxt = 3'bxxx;
                wb_fsm_state_nxt = 2'bxx;
        end
        endcase
end
 
//
// WB FSM - output signals
// 
always @(posedge wb_clk_i or posedge wb_rst_i) begin
        if (wb_rst_i) begin
                wb_cyc_o        <= #1 1'b0;
                wb_stb_o        <= #1 1'b0;
                wb_cti_o        <= #1 3'b111;
                wb_bte_o        <= #1 2'b01;    // 4-beat wrap burst = constant
`ifdef OR1200_WB_CAB
                wb_cab_o        <= #1 1'b0;
`endif
                wb_we_o         <= #1 1'b0;
                wb_sel_o        <= #1 4'hf;
                wb_adr_o        <= #1 {aw{1'b0}};
                wb_dat_o        <= #1 {dw{1'b0}};
        end
        else begin
                wb_cyc_o        <= #1 wb_cyc_nxt;
//              wb_stb_o        <= #1 wb_stb_nxt;
                if (wb_ack && wb_cti_o == 3'b111)
                        wb_stb_o        <= #1 1'b0;
                else
                        wb_stb_o        <= #1 wb_stb_nxt;
                wb_cti_o        <= #1 wb_cti_nxt;
                wb_bte_o        <= #1 2'b01;    // 4-beat wrap burst = constant
`ifdef OR1200_WB_CAB
                wb_cab_o        <= #1 biu_cab_i;
`endif
                // we and sel - set at beginning of access 
                if (wb_fsm_state_cur == wb_fsm_idle) begin
                        wb_we_o         <= #1 biu_we_i;
                        wb_sel_o        <= #1 biu_sel_i;
                end
                // adr - set at beginning of access and changed at every termination 
                if (wb_fsm_state_cur == wb_fsm_idle) begin
                   wb_adr_o     <= #1 biu_adr_i;
                end
                else if (wb_stb_o && wb_ack) begin
                        wb_adr_o[3:2]   <= #1 wb_adr_o[3:2] + 1'b1;
                end
                // dat - write data changed after avery subsequent write access
                if (!wb_stb_o) begin
                        wb_dat_o        <= #1 biu_dat_i;
                end
        end
end
 
//
// WB & BIU termination toggle counters
// 
always @(posedge wb_clk_i or posedge wb_rst_i) begin
        if (wb_rst_i) begin
                wb_ack_cnt      <= #1 1'b0;
                wb_err_cnt      <= #1 1'b0;
                wb_rty_cnt      <= #1 1'b0;
        end
        else begin
                // WB ack toggle counter
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
                        wb_ack_cnt      <= #1 1'b0;
                else if (wb_stb_o && wb_ack)
                        wb_ack_cnt      <= #1 !wb_ack_cnt;
                // WB err toggle counter
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
                        wb_err_cnt      <= #1 1'b0;
                else if (wb_stb_o && wb_err_i)
                        wb_err_cnt      <= #1 !wb_err_cnt;
                // WB rty toggle counter
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
                        wb_rty_cnt      <= #1 1'b0;
                else if (wb_stb_o && wb_rty_i)
                        wb_rty_cnt      <= #1 !wb_rty_cnt;
        end
end
 
always @(posedge clk or posedge rst) begin
        if (rst) begin
                biu_stb_reg     <= #1 1'b0;
                biu_ack_cnt     <= #1 1'b0;
                biu_err_cnt     <= #1 1'b0;
                biu_rty_cnt     <= #1 1'b0;
`ifdef OR1200_WB_RETRY
                retry_cnt       <= {`OR1200_WB_RETRY{1'b0}};
`endif
        end
        else begin
                // BIU strobe
                if (biu_stb_i && !biu_cab_i && biu_ack_o)
                        biu_stb_reg     <= #1 1'b0;
                else
                        biu_stb_reg     <= #1 biu_stb_i;
                // BIU ack toggle counter
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
                        biu_ack_cnt     <= #1 1'b0 ;
                else if (biu_ack_o)
                        biu_ack_cnt     <= #1 !biu_ack_cnt ;
                // BIU err toggle counter
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
                        biu_err_cnt     <= #1 1'b0 ;
                else if (wb_err_i && biu_err_o)
                        biu_err_cnt     <= #1 !biu_err_cnt ;
                // BIU rty toggle counter
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
                        biu_rty_cnt     <= #1 1'b0 ;
                else if (biu_rty)
                        biu_rty_cnt     <= #1 !biu_rty_cnt ;
`ifdef OR1200_WB_RETRY
                if (biu_ack_o || biu_err_o)
                        retry_cnt       <= #1 {`OR1200_WB_RETRY{1'b0}};
                else if (biu_rty)
                        retry_cnt       <= #1 retry_cnt + 1'b1;
`endif
        end
end
 
assign biu_stb = biu_stb_i && biu_stb_reg;
 
//
// Input BIU data bus
//
assign  biu_dat_o       = wb_dat_i;
 
//
// Input BIU termination signals 
//
assign  biu_rty         = (wb_fsm_state_cur == wb_fsm_trans) && wb_rty_i && wb_stb_o && (wb_rty_cnt ~^ biu_rty_cnt);
assign  biu_ack_o       = (wb_fsm_state_cur == wb_fsm_trans) && wb_ack && wb_stb_o && (wb_ack_cnt ~^ biu_ack_cnt);
assign  biu_err_o       = (wb_fsm_state_cur == wb_fsm_trans) && wb_err_i && wb_stb_o && (wb_err_cnt ~^ biu_err_cnt)
`ifdef OR1200_WB_RETRY
                        || biu_rty && retry_cnt[`OR1200_WB_RETRY-1];
`else
                        ;
`endif
 
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's WISHBONE BIU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implements WISHBONE interface ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - if biu_cyc/stb are deasserted and wb_ack_i is asserted ////`
13			`//// and this happens even before aborted_r is asssrted, ////`
14			`//// wb_ack_i will be delivered even though transfer is ////`
15			`//// internally considered already aborted. However most ////`
16			`//// wb_ack_i are externally registered and delayed. Normally ////`
17			`//// this shouldn't cause any problems. ////`
18			`//// ////`
19			`//// Author(s): ////`
20			`//// - Damjan Lampret, lampret@opencores.org ////`
21			`//// ////`
22			`//////////////////////////////////////////////////////////////////////`
23			`//// ////`
24			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from http://www.opencores.org/lgpl.shtml ////`
46			`//// ////`
47			`//////////////////////////////////////////////////////////////////////`
48			`//`
49			`// CVS Revision History`
50			`//`
51	142	marcus.erl	`// $Log: or1200_wb_biu.v,v $`
52			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
53			`// Major update:`
54			`// Structure reordered and bugs fixed.`
55			`//`
56			`// Revision 1.7 2004/04/05 08:29:57 lampret`
57			`// Merged branch_qmem into main tree.`
58			`//`
59	10	unneback	`// Revision 1.6.4.1 2003/07/08 15:36:37 lampret`
60			`// Added embedded memory QMEM.`
61			`//`
62			`// Revision 1.6 2003/04/07 20:57:46 lampret`
63			`// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.`
64			`//`
65			`// Revision 1.5 2002/12/08 08:57:56 lampret`
66			`// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.`
67			`//`
68			`// Revision 1.4 2002/09/16 03:09:16 lampret`
69			`// Fixed a combinational loop.`
70			`//`
71			`// Revision 1.3 2002/08/12 05:31:37 lampret`
72			`// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.`
73			`//`
74			`// Revision 1.2 2002/07/14 22:17:17 lampret`
75			`// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.`
76			`//`
77			`// Revision 1.1 2002/01/03 08:16:15 lampret`
78			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
79			`//`
80			`// Revision 1.12 2001/11/22 13:42:51 lampret`
81			`// Added wb_cyc_o assignment after it was removed by accident.`
82			`//`
83			`// Revision 1.11 2001/11/20 21:28:10 lampret`
84			`// Added optional sampling of inputs.`
85			`//`
86			`// Revision 1.10 2001/11/18 11:32:00 lampret`
87			`// OR1200_REGISTERED_OUTPUTS can now be enabled.`
88			`//`
89			`// Revision 1.9 2001/10/21 17:57:16 lampret`
90			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
91			`//`
92			`// Revision 1.8 2001/10/14 13:12:10 lampret`
93			`// MP3 version.`
94			`//`
95			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
96			`// no message`
97			`//`
98			`// Revision 1.3 2001/08/09 13:39:33 lampret`
99			`// Major clean-up.`
100			`//`
101			`// Revision 1.2 2001/07/22 03:31:54 lampret`
102			`// Fixed RAM's oen bug. Cache bypass under development.`
103			`//`
104			`// Revision 1.1 2001/07/20 00:46:23 lampret`
105			`// Development version of RTL. Libraries are missing.`
106			`//`
107			`//`
108
109			`// synopsys translate_off`
110			`include "timescale.v"
111			`// synopsys translate_on`
112			`include "or1200_defines.v"
113
114			`module or1200_wb_biu(`
115			`// RISC clock, reset and clock control`
116			`clk, rst, clmode,`
117
118			`// WISHBONE interface`
119			`wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,`
120			`wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,`
121			`ifdef OR1200_WB_CAB
122			`wb_cab_o,`
123			`endif
124			`ifdef OR1200_WB_B3
125			`wb_cti_o, wb_bte_o,`
126			`endif
127
128			`// Internal RISC bus`
129			`biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,`
130			`biu_dat_o, biu_ack_o, biu_err_o`
131			`);`
132
133			parameter dw = `OR1200_OPERAND_WIDTH;
134			parameter aw = `OR1200_OPERAND_WIDTH;
135
136			`//`
137			`// RISC clock, reset and clock control`
138			`//`
139	142	marcus.erl	`input clk; // RISC clock`
140			`input rst; // RISC reset`
141			`input [1:0] clmode; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4`
142	10	unneback
143			`//`
144			`// WISHBONE interface`
145			`//`
146	142	marcus.erl	`input wb_clk_i; // clock input`
147			`input wb_rst_i; // reset input`
148			`input wb_ack_i; // normal termination`
149			`input wb_err_i; // termination w/ error`
150			`input wb_rty_i; // termination w/ retry`
151			`input [dw-1:0] wb_dat_i; // input data bus`
152			`output wb_cyc_o; // cycle valid output`
153			`output [aw-1:0] wb_adr_o; // address bus outputs`
154			`output wb_stb_o; // strobe output`
155			`output wb_we_o; // indicates write transfer`
156			`output [3:0] wb_sel_o; // byte select outputs`
157			`output [dw-1:0] wb_dat_o; // output data bus`
158	10	unneback	`ifdef OR1200_WB_CAB
159	142	marcus.erl	`output wb_cab_o; // consecutive address burst`
160	10	unneback	`endif
161			`ifdef OR1200_WB_B3
162	142	marcus.erl	`output [2:0] wb_cti_o; // cycle type identifier`
163			`output [1:0] wb_bte_o; // burst type extension`
164	10	unneback	`endif
165
166			`//`
167			`// Internal RISC interface`
168			`//`
169	142	marcus.erl	`input [dw-1:0] biu_dat_i; // input data bus`
170			`input [aw-1:0] biu_adr_i; // address bus`
171			`input biu_cyc_i; // WB cycle`
172			`input biu_stb_i; // WB strobe`
173			`input biu_we_i; // WB write enable`
174			`input biu_cab_i; // CAB input`
175			`input [3:0] biu_sel_i; // byte selects`
176			`output [31:0] biu_dat_o; // output data bus`
177			`output biu_ack_o; // ack output`
178			`output biu_err_o; // err output`
179	10	unneback
180			`//`
181			`// Registers`
182			`//`
183	142	marcus.erl	`wire wb_ack; // normal termination`
184			`reg [aw-1:0] wb_adr_o; // address bus outputs`
185			`reg wb_cyc_o; // cycle output`
186			`reg wb_stb_o; // strobe output`
187			`reg wb_we_o; // indicates write transfer`
188			`reg [3:0] wb_sel_o; // byte select outputs`
189	10	unneback	`ifdef OR1200_WB_CAB
190	142	marcus.erl	`reg wb_cab_o; // CAB output`
191	10	unneback	`endif
192			`ifdef OR1200_WB_B3
193	142	marcus.erl	`reg [2:0] wb_cti_o; // cycle type identifier`
194			`reg [1:0] wb_bte_o; // burst type extension`
195	10	unneback	`endif
196	142	marcus.erl	`reg [dw-1:0] wb_dat_o; // output data bus`
197
198	10	unneback	`ifdef OR1200_WB_RETRY
199	142	marcus.erl	reg [`OR1200_WB_RETRY-1:0] retry_cnt; // Retry counter
200	10	unneback	`else
201	142	marcus.erl	`wire retry_cnt = 1'b0;`
202	10	unneback	`endif
203	142	marcus.erl	`ifdef OR1200_WB_B3
204			`reg [1:0] burst_len; // burst counter`
205	10	unneback	`endif
206
207	142	marcus.erl	`reg biu_stb_reg; // WB strobe`
208			`wire biu_stb; // WB strobe`
209			`reg wb_cyc_nxt; // next WB cycle value`
210			`reg wb_stb_nxt; // next WB strobe value`
211			`reg [2:0] wb_cti_nxt; // next cycle type identifier value`
212	10	unneback
213	142	marcus.erl	`reg wb_ack_cnt; // WB ack toggle counter`
214			`reg wb_err_cnt; // WB err toggle counter`
215			`reg wb_rty_cnt; // WB rty toggle counter`
216			`reg biu_ack_cnt; // BIU ack toggle counter`
217			`reg biu_err_cnt; // BIU err toggle counter`
218			`reg biu_rty_cnt; // BIU rty toggle counter`
219			`wire biu_rty; // BIU rty indicator`
220	10	unneback
221	142	marcus.erl	`reg [1:0] wb_fsm_state_cur; // WB FSM - surrent state`
222			`reg [1:0] wb_fsm_state_nxt; // WB FSM - next state`
223			`wire [1:0] wb_fsm_idle = 2'h0; // WB FSM state - IDLE`
224			`wire [1:0] wb_fsm_trans = 2'h1; // WB FSM state - normal TRANSFER`
225			`wire [1:0] wb_fsm_last = 2'h2; // EB FSM state - LAST transfer`
226	10	unneback
227			`//`
228	142	marcus.erl	`// WISHBONE I/F <-> Internal RISC I/F conversion`
229	10	unneback	`//`
230	142	marcus.erl	`//assign wb_ack = wb_ack_i;`
231			`assign wb_ack = wb_ack_i && !wb_err_i && !wb_rty_i;`
232	10	unneback
233			`//`
234	142	marcus.erl	`// WB FSM - register part`
235			`//`
236			`always @(posedge wb_clk_i or posedge wb_rst_i) begin`
237			`if (wb_rst_i)`
238			`wb_fsm_state_cur <= #1 wb_fsm_idle;`
239			`else`
240			`wb_fsm_state_cur <= #1 wb_fsm_state_nxt;`
241			`end`
242	10	unneback
243			`//`
244	142	marcus.erl	`// WB burst tength counter`
245			`//`
246			`always @(posedge wb_clk_i or posedge wb_rst_i) begin`
247			`if (wb_rst_i) begin`
248			`burst_len <= #1 2'h0;`
249			`end`
250			`else begin`
251			`// burst counter`
252			`if (wb_fsm_state_cur == wb_fsm_idle)`
253			`burst_len <= #1 2'h2;`
254			`else if (wb_stb_o && wb_ack)`
255			`burst_len <= #1 burst_len - 1'b1;`
256			`end`
257			`end`
258	10	unneback
259			`//`
260	142	marcus.erl	`// WB FSM - combinatorial part`
261			`//`
262			`always @(wb_fsm_state_cur or burst_len or`
263			`wb_err_i or wb_rty_i or wb_ack or wb_cti_o or wb_sel_o or wb_stb_o or wb_we_o or`
264			`biu_cyc_i or biu_stb or biu_cab_i or biu_sel_i or biu_we_i) begin`
265			`// States of WISHBONE Finite State Machine`
266			`case(wb_fsm_state_cur)`
267			`// IDLE`
268			`wb_fsm_idle : begin`
269			`wb_cyc_nxt = biu_cyc_i && biu_stb;`
270			`wb_stb_nxt = biu_cyc_i && biu_stb;`
271			`wb_cti_nxt = {!biu_cab_i, 1'b1, !biu_cab_i};`
272			`if (biu_cyc_i && biu_stb)`
273			`wb_fsm_state_nxt = wb_fsm_trans;`
274			`else`
275			`wb_fsm_state_nxt = wb_fsm_idle;`
276			`end`
277			`// normal TRANSFER`
278			`wb_fsm_trans : begin`
279			`wb_cyc_nxt = !wb_stb_o \|\| !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);`
280			`wb_stb_nxt = !wb_stb_o \|\| !wb_err_i && !wb_rty_i && !wb_ack \|\| !wb_err_i && !wb_rty_i && wb_cti_o == 3'b010 && !wb_we_o;`
281			`wb_cti_nxt[2] = wb_stb_o && wb_ack && burst_len == 'h0 \|\| wb_cti_o[2];`
282			`wb_cti_nxt[1] = 1'b1 ;`
283			`wb_cti_nxt[0] = wb_stb_o && wb_ack && burst_len == 'h0 \|\| wb_cti_o[0];`
284			`//if ((!biu_cyc_i \|\| !biu_stb \|\| !biu_cab_i) && wb_cti_o == 3'b010 \|\| biu_sel_i != wb_sel_o \|\| biu_we_i != wb_we_o)`
285			`if ((!biu_cyc_i \|\| !biu_stb \|\| !biu_cab_i \|\| biu_sel_i != wb_sel_o \|\| biu_we_i != wb_we_o) && wb_cti_o == 3'b010)`
286			`wb_fsm_state_nxt = wb_fsm_last;`
287			`else if ((wb_err_i \|\| wb_rty_i \|\| wb_ack && wb_cti_o == 3'b111) && wb_stb_o)`
288			`wb_fsm_state_nxt = wb_fsm_idle;`
289			`else`
290			`wb_fsm_state_nxt = wb_fsm_trans;`
291			`end`
292			`// LAST transfer`
293			`wb_fsm_last : begin`
294			`wb_cyc_nxt = !wb_stb_o \|\| !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);`
295			`wb_stb_nxt = !wb_stb_o \|\| !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);`
296			`wb_cti_nxt[2] = wb_ack && wb_stb_o \|\| wb_cti_o[2];`
297			`wb_cti_nxt[1] = 1'b1 ;`
298			`wb_cti_nxt[0] = wb_ack && wb_stb_o \|\| wb_cti_o[0];`
299			`if ((wb_err_i \|\| wb_rty_i \|\| wb_ack && wb_cti_o == 3'b111) && wb_stb_o)`
300			`wb_fsm_state_nxt = wb_fsm_idle;`
301			`else`
302			`wb_fsm_state_nxt = wb_fsm_last;`
303			`end`
304			`// default state`
305			`default:begin`
306			`wb_cyc_nxt = 1'bx;`
307			`wb_stb_nxt = 1'bx;`
308			`wb_cti_nxt = 3'bxxx;`
309			`wb_fsm_state_nxt = 2'bxx;`
310			`end`
311			`endcase`
312			`end`
313	10	unneback
314			`//`
315	142	marcus.erl	`// WB FSM - output signals`
316	10	unneback	`//`
317	142	marcus.erl	`always @(posedge wb_clk_i or posedge wb_rst_i) begin`
318			`if (wb_rst_i) begin`
319			`wb_cyc_o <= #1 1'b0;`
320			`wb_stb_o <= #1 1'b0;`
321			`wb_cti_o <= #1 3'b111;`
322			`wb_bte_o <= #1 2'b01; // 4-beat wrap burst = constant`
323			`ifdef OR1200_WB_CAB
324			`wb_cab_o <= #1 1'b0;`
325	10	unneback	`endif
326	142	marcus.erl	`wb_we_o <= #1 1'b0;`
327			`wb_sel_o <= #1 4'hf;`
328			`wb_adr_o <= #1 {aw{1'b0}};`
329			`wb_dat_o <= #1 {dw{1'b0}};`
330			`end`
331			`else begin`
332			`wb_cyc_o <= #1 wb_cyc_nxt;`
333			`// wb_stb_o <= #1 wb_stb_nxt;`
334			`if (wb_ack && wb_cti_o == 3'b111)`
335			`wb_stb_o <= #1 1'b0;`
336			`else`
337			`wb_stb_o <= #1 wb_stb_nxt;`
338			`wb_cti_o <= #1 wb_cti_nxt;`
339			`wb_bte_o <= #1 2'b01; // 4-beat wrap burst = constant`
340			`ifdef OR1200_WB_CAB
341			`wb_cab_o <= #1 biu_cab_i;`
342	10	unneback	`endif
343	142	marcus.erl	`// we and sel - set at beginning of access`
344			`if (wb_fsm_state_cur == wb_fsm_idle) begin`
345			`wb_we_o <= #1 biu_we_i;`
346			`wb_sel_o <= #1 biu_sel_i;`
347			`end`
348			`// adr - set at beginning of access and changed at every termination`
349			`if (wb_fsm_state_cur == wb_fsm_idle) begin`
350			`wb_adr_o <= #1 biu_adr_i;`
351			`end`
352			`else if (wb_stb_o && wb_ack) begin`
353			`wb_adr_o[3:2] <= #1 wb_adr_o[3:2] + 1'b1;`
354			`end`
355			`// dat - write data changed after avery subsequent write access`
356			`if (!wb_stb_o) begin`
357			`wb_dat_o <= #1 biu_dat_i;`
358			`end`
359			`end`
360			`end`
361	10	unneback
362			`//`
363	142	marcus.erl	`// WB & BIU termination toggle counters`
364			`//`
365			`always @(posedge wb_clk_i or posedge wb_rst_i) begin`
366			`if (wb_rst_i) begin`
367			`wb_ack_cnt <= #1 1'b0;`
368			`wb_err_cnt <= #1 1'b0;`
369			`wb_rty_cnt <= #1 1'b0;`
370			`end`
371			`else begin`
372			`// WB ack toggle counter`
373			`if (wb_fsm_state_cur == wb_fsm_idle \|\| !clmode)`
374			`wb_ack_cnt <= #1 1'b0;`
375			`else if (wb_stb_o && wb_ack)`
376			`wb_ack_cnt <= #1 !wb_ack_cnt;`
377			`// WB err toggle counter`
378			`if (wb_fsm_state_cur == wb_fsm_idle \|\| !clmode)`
379			`wb_err_cnt <= #1 1'b0;`
380			`else if (wb_stb_o && wb_err_i)`
381			`wb_err_cnt <= #1 !wb_err_cnt;`
382			`// WB rty toggle counter`
383			`if (wb_fsm_state_cur == wb_fsm_idle \|\| !clmode)`
384			`wb_rty_cnt <= #1 1'b0;`
385			`else if (wb_stb_o && wb_rty_i)`
386			`wb_rty_cnt <= #1 !wb_rty_cnt;`
387			`end`
388			`end`
389	10	unneback
390	142	marcus.erl	`always @(posedge clk or posedge rst) begin`
391			`if (rst) begin`
392			`biu_stb_reg <= #1 1'b0;`
393			`biu_ack_cnt <= #1 1'b0;`
394			`biu_err_cnt <= #1 1'b0;`
395			`biu_rty_cnt <= #1 1'b0;`
396			`ifdef OR1200_WB_RETRY
397			retry_cnt <= {`OR1200_WB_RETRY{1'b0}};
398	10	unneback	`endif
399	142	marcus.erl	`end`
400			`else begin`
401			`// BIU strobe`
402			`if (biu_stb_i && !biu_cab_i && biu_ack_o)`
403			`biu_stb_reg <= #1 1'b0;`
404			`else`
405			`biu_stb_reg <= #1 biu_stb_i;`
406			`// BIU ack toggle counter`
407			`if (wb_fsm_state_cur == wb_fsm_idle \|\| !clmode)`
408			`biu_ack_cnt <= #1 1'b0 ;`
409			`else if (biu_ack_o)`
410			`biu_ack_cnt <= #1 !biu_ack_cnt ;`
411			`// BIU err toggle counter`
412			`if (wb_fsm_state_cur == wb_fsm_idle \|\| !clmode)`
413			`biu_err_cnt <= #1 1'b0 ;`
414			`else if (wb_err_i && biu_err_o)`
415			`biu_err_cnt <= #1 !biu_err_cnt ;`
416			`// BIU rty toggle counter`
417			`if (wb_fsm_state_cur == wb_fsm_idle \|\| !clmode)`
418			`biu_rty_cnt <= #1 1'b0 ;`
419			`else if (biu_rty)`
420			`biu_rty_cnt <= #1 !biu_rty_cnt ;`
421			`ifdef OR1200_WB_RETRY
422			`if (biu_ack_o \|\| biu_err_o)`
423			retry_cnt <= #1 {`OR1200_WB_RETRY{1'b0}};
424			`else if (biu_rty)`
425			`retry_cnt <= #1 retry_cnt + 1'b1;`
426	10	unneback	`endif
427	142	marcus.erl	`end`
428			`end`
429	10	unneback
430	142	marcus.erl	`assign biu_stb = biu_stb_i && biu_stb_reg;`
431	10	unneback
432			`//`
433	142	marcus.erl	`// Input BIU data bus`
434	10	unneback	`//`
435	142	marcus.erl	`assign biu_dat_o = wb_dat_i;`
436	10	unneback
437			`//`
438	142	marcus.erl	`// Input BIU termination signals`
439	10	unneback	`//`
440	142	marcus.erl	`assign biu_rty = (wb_fsm_state_cur == wb_fsm_trans) && wb_rty_i && wb_stb_o && (wb_rty_cnt ~^ biu_rty_cnt);`
441			`assign biu_ack_o = (wb_fsm_state_cur == wb_fsm_trans) && wb_ack && wb_stb_o && (wb_ack_cnt ~^ biu_ack_cnt);`
442			`assign biu_err_o = (wb_fsm_state_cur == wb_fsm_trans) && wb_err_i && wb_stb_o && (wb_err_cnt ~^ biu_err_cnt)`
443			`ifdef OR1200_WB_RETRY
444			\|\| biu_rty && retry_cnt[`OR1200_WB_RETRY-1];
445	10	unneback	`else
446	142	marcus.erl	`;`
447	10	unneback	`endif
448
449
450			`endmodule`

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