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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_wbmux.v] - Blame information for rev 797

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Write-back Mux                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  CPU's write-back stage of the pipeline                      ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
//
// $Log: or1200_wbmux.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// No update 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_wbmux(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        wb_freeze, rfwb_op,
        muxin_a, muxin_b, muxin_c, muxin_d, muxin_e,
        muxout, muxreg, muxreg_valid
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Internal i/f
//
input                           wb_freeze;
input   [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op;
input   [width-1:0]              muxin_a;
input   [width-1:0]              muxin_b;
input   [width-1:0]              muxin_c;
input   [width-1:0]              muxin_d;
input   [width-1:0]              muxin_e;
output  [width-1:0]              muxout;
output  [width-1:0]              muxreg;
output                          muxreg_valid;
 
//
// Internal wires and regs
//
reg     [width-1:0]              muxout;
reg     [width-1:0]              muxreg;
reg                             muxreg_valid;
 
//
// Registered output from the write-back multiplexer
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
        if (rst == `OR1200_RST_VALUE) begin
                muxreg <=  32'd0;
                muxreg_valid <=  1'b0;
        end
        else if (!wb_freeze) begin
                muxreg <=  muxout;
                muxreg_valid <=  rfwb_op[0];
        end
end
 
//
// Write-back multiplexer
//
always @(muxin_a or muxin_b or muxin_c or muxin_d or muxin_e or rfwb_op) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        casez(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
`else
        casez(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
`endif
                `OR1200_RFWBOP_ALU: muxout = muxin_a;
                `OR1200_RFWBOP_LSU: begin
                        muxout = muxin_b;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("  WBMUX: muxin_b %h", muxin_b);
// synopsys translate_on
`endif
                end
                `OR1200_RFWBOP_SPRS: begin
                        muxout = muxin_c;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("  WBMUX: muxin_c %h", muxin_c);
// synopsys translate_on
`endif
                end
                `OR1200_RFWBOP_LR: begin
                        muxout = muxin_d + 32'h8;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("  WBMUX: muxin_d %h", muxin_d + 4'h8);
// synopsys translate_on
`endif
                end
`ifdef OR1200_FPU_IMPLEMENTED
                `OR1200_RFWBOP_FPU : begin
             muxout = muxin_e;
 `ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("  WBMUX: muxin_e %h", muxin_e);
// synopsys translate_on
`endif
               end
`endif
          default : begin
             muxout = 0;
          end
 
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Write-back Mux ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6	185	julius	`//// http://www.opencores.org/project,or1k ////`
7	10	unneback	`//// ////`
8			`//// Description ////`
9			`//// CPU's write-back stage of the pipeline ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`//`
45	142	marcus.erl	`// $Log: or1200_wbmux.v,v $`
46			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
47			`// No update`
48	10	unneback
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52			`include "or1200_defines.v"
53
54			`module or1200_wbmux(`
55			`// Clock and reset`
56			`clk, rst,`
57
58			`// Internal i/f`
59			`wb_freeze, rfwb_op,`
60	185	julius	`muxin_a, muxin_b, muxin_c, muxin_d, muxin_e,`
61	10	unneback	`muxout, muxreg, muxreg_valid`
62			`);`
63
64			parameter width = `OR1200_OPERAND_WIDTH;
65
66			`//`
67			`// I/O`
68			`//`
69
70			`//`
71			`// Clock and reset`
72			`//`
73			`input clk;`
74			`input rst;`
75
76			`//`
77			`// Internal i/f`
78			`//`
79			`input wb_freeze;`
80			input [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
81			`input [width-1:0] muxin_a;`
82			`input [width-1:0] muxin_b;`
83			`input [width-1:0] muxin_c;`
84			`input [width-1:0] muxin_d;`
85	185	julius	`input [width-1:0] muxin_e;`
86	10	unneback	`output [width-1:0] muxout;`
87			`output [width-1:0] muxreg;`
88			`output muxreg_valid;`
89
90			`//`
91			`// Internal wires and regs`
92			`//`
93			`reg [width-1:0] muxout;`
94			`reg [width-1:0] muxreg;`
95			`reg muxreg_valid;`
96
97			`//`
98			`// Registered output from the write-back multiplexer`
99			`//`
100	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
101			if (rst == `OR1200_RST_VALUE) begin
102	258	julius	`muxreg <= 32'd0;`
103			`muxreg_valid <= 1'b0;`
104	10	unneback	`end`
105			`else if (!wb_freeze) begin`
106	258	julius	`muxreg <= muxout;`
107			`muxreg_valid <= rfwb_op[0];`
108	10	unneback	`end`
109			`end`
110
111			`//`
112			`// Write-back multiplexer`
113			`//`
114	185	julius	`always @(muxin_a or muxin_b or muxin_c or muxin_d or muxin_e or rfwb_op) begin`
115	10	unneback	`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
116	364	julius	casez(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
117	10	unneback	`else
118	364	julius	casez(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
119	10	unneback	`endif
120	185	julius	`OR1200_RFWBOP_ALU: muxout = muxin_a;
121			`OR1200_RFWBOP_LSU: begin
122	10	unneback	`muxout = muxin_b;`
123			`ifdef OR1200_VERBOSE
124			`// synopsys translate_off`
125			`$display(" WBMUX: muxin_b %h", muxin_b);`
126			`// synopsys translate_on`
127			`endif
128			`end`
129	185	julius	`OR1200_RFWBOP_SPRS: begin
130	10	unneback	`muxout = muxin_c;`
131			`ifdef OR1200_VERBOSE
132			`// synopsys translate_off`
133			`$display(" WBMUX: muxin_c %h", muxin_c);`
134			`// synopsys translate_on`
135			`endif
136			`end`
137	185	julius	`OR1200_RFWBOP_LR: begin
138	10	unneback	`muxout = muxin_d + 32'h8;`
139			`ifdef OR1200_VERBOSE
140			`// synopsys translate_off`
141			`$display(" WBMUX: muxin_d %h", muxin_d + 4'h8);`
142			`// synopsys translate_on`
143			`endif
144			`end`
145	185	julius	`ifdef OR1200_FPU_IMPLEMENTED
146			`OR1200_RFWBOP_FPU : begin
147			`muxout = muxin_e;`
148			`ifdef OR1200_VERBOSE
149			`// synopsys translate_off`
150			`$display(" WBMUX: muxin_e %h", muxin_e);`
151			`// synopsys translate_on`
152			`endif
153			`end`
154	364	julius	`endif
155			`default : begin`
156			`muxout = 0;`
157			`end`
158
159	10	unneback	`endcase`
160			`end`
161
162			`endmodule`

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_wbmux.v] - Blame information for rev 797